ADSP-2181KSZ-160 Analog Devices Inc, ADSP-2181KSZ-160 Datasheet - Page 18

IC DSP CONTROLLER 16BIT 128-PQFP

ADSP-2181KSZ-160

Manufacturer Part Number
ADSP-2181KSZ-160
Description
IC DSP CONTROLLER 16BIT 128-PQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2181KSZ-160

Interface
Synchronous Serial Port (SSP)
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
No. Of Bits
16
Frequency
40MHz
Supply Voltage
5V
Embedded Interface Type
Host Port, Serial
No. Of Mips
40
Supply Voltage Range
4.5V To 5.5V
Operating Temperature Range
0°C To
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
32KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
MQFP
Package
128MQFP
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
40 MHz
Device Million Instructions Per Second
40 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2181KSZ-160
Manufacturer:
MICROCHIP
Quantity:
101
Part Number:
ADSP-2181KSZ-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2181KSZ-160
Manufacturer:
AD
Quantity:
20 000
ADSP-2181
Parameter
Memory Write
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
w = wait states
xMS = PMS, DMS, CMS, IOMS, BMS.
DW
DH
WP
WDE
ASW
DDR
CWR
AW
WRA
WWR
t
CK
.
Data Setup before WR High
Data Hold after WR High
WR Pulsewidth
WR Low to Data Enabled
A0–A13, xMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, xMS, Setup before WR Deasserted
A0–A13, xMS Hold after WR Deasserted
WR High to RD or WR Low
DMS, PMS,
BMS, CMS,
CLKOUT
A0–A13
IOMS
WR
RD
D
Figure 12. Memory Write
t
CWR
t
ASW
–18–
t
WDE
t
AW
t
WP
Min
0.5t
0.25t
0.5t
0
0.25t
0.25t
0.25t
0.75t
0.25t
0.5t
t
DW
CK
CK
CK
CK
CK
CK
CK
CK
CK
– 7 + w
– 5 + w
– 5
– 2
– 4
– 5
– 9 + w
– 3
– 4
t
WRA
t
DH
t
WWR
t
DDR
Max
0.25 t
CK
+ 7
REV. D
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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