ADSP-21061LKS-176 Analog Devices Inc, ADSP-21061LKS-176 Datasheet - Page 31

• Manufacturer Part Number: ADSP-21061LKS-176
• Description: IC DSP CONTROLLER 1MBIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKS-176

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 44MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP

Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21061s (BRx) or a host processor, both
synchronous and asynchronous (HBR, HBG).
Table 16. Multiprocessor Bus Request and Host Bus Request
1
2
3
4
5
6
7
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 t
Only required for recognition in the current cycle.
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
For the ADSP-21061L (3.3 V), this specification is 8.5 – DT/8 ns max.
(O/D) = open drain, (A/D) = active drive.
For the ADSP-21061L (3.3 V), this specification is 12 ns max.
For the ADSP-21061L (3.3 V), this specification is 40 + 23DT/16 ns min.
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
SRPBAI
HRPBAI
DHBGO
HHBGO
DBRO
HBRO
DCPAO
TRCPA
DRDYCS
TRDYHG
ARDYTR
easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21061” section in the ADSP-21061 SHARC
User’s Manual, Revision 2.1.
HBG Low to RD/WR/CS Valid
HBR Setup Before CLKIN
HBR Hold After CLKIN
HBG Setup Before CLKIN
HBG Hold After CLKIN High
BRx, CPA Setup Before CLKIN
BRx, CPA Hold After CLKIN High
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
2
2
4
1
3
Rev. C | Page 31 of 56 | July 2007
5
5, 6
5, 7
CK
before RD or WR goes low or by t
Min
20 + 3DT/4
13 + DT/2
13 + DT/2
20 + 3DT/4
–2 – DT/8
–2 – DT/8
–2 – DT/8
44 + 27DT/16
ADSP-21061/ADSP-21061L
5 V and 3.3 V
HBGRCSV
Max
20 + 5DT/4
14 + 3DT/4
6 + DT/2
6 + DT/2
12 + 3DT/4
5.5 – DT/8
6.5 – DT/8
4.5 – DT/8
8
10
7 – DT/8
after HBG goes low. This is
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns