ADSP-2185KST-133 Analog Devices Inc, ADSP-2185KST-133 Datasheet - Page 14

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ADSP-2185KST-133

Manufacturer Part Number
ADSP-2185KST-133
Description
IC DSP CONTROLLER 16BIT 100TQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2185KST-133

Rohs Status
RoHS non-compliant
Interface
Host Interface, Serial Port
Clock Rate
33.3MHz
Non-volatile Memory
External
On-chip Ram
80kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP

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ESD SENSITIVITY
The ADSP-2185 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-2185 features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality. Unused devices must be stored in
conductive foam or shunts, and the foam should be discharged to the destination before devices are
removed.
ADSP-2185
ADSP-2185 TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V
Operating Temperature Range (Ambient) . . –40 C to +85 C
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . +280 C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DD
DD
+ 0.3 V
+ 0.3 V
–14–
MEMORY TIMING SPECIFICATIONS
The table below shows common memory device specifications
and the corresponding ADSP-2185 timing parameters, for your
convenience.
Memory
Device
Specification
Address Setup to
Address Setup to
Address Hold Time
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time t
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
t
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). t
0.5t
meters to obtain the specification value.
Example: t
CK
Write Start
Write End
is defined as 0.5t
CKI
period should be substituted for all relevant timing para-
CKH
= 0.5t
CKI
CK
ADSP-2185 Timing
Timing
Parameter
t
t
t
t
t
t
ASW
AW
WRA
DW
DH
RDD
AA
. The ADSP-2185 uses an input clock
– 7 ns = 0.5 (30 ns) – 7 ns = 8 ns
WARNING!
CK
Parameter
Definition
A0-A13, xMS Setup
before WR Low
A0-A13, xMS Setup
before WR Deasserted
A0-A13, xMS Hold before
WR Low
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0-A13, xMS to Data
Valid
values within the range of
ESD SENSITIVE DEVICE
REV. 0

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