ADSP-21369KSZ-1A Analog Devices Inc, ADSP-21369KSZ-1A Datasheet - Page 41

• Manufacturer Part Number: ADSP-21369KSZ-1A
• Description: IC DSP 32BIT 266 MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21369KSZ-1A

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (768 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 266MHz
• Mips: 266
• Device Input Clock Speed: 266MHz
• Ram Size: 256KB
• Program Memory Size: 768KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: MQFP
• For Use With: ADZS-21369-EZLITE - KIT EVAL EZ LITE ADDS-21369
• Lead Free Status / Rohs Status: Compliant
• Other names: Q2886718

Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 36. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
SRCSFS
SRCHFS
SRCCLKW
SRCCLK
SRCTDD
SRCTDH
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
Clock Width
Clock Period
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
DAI_P20–1
DAI_P20–1
DAI_P20–1
(SDATA)
(SCLK)
(FS)
t
SRCTDH
Figure 29. SRC Serial Output Port Timing
t
SRCTDD
Rev. E | Page 41 of 60 | July 2009
t
SRCCLKW
t
SRCSFS
SAMPLE EDGE
ADSP-21367/ADSP-21368/ADSP-21369
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
t
SRCHFS
t
SRCCLK
Min
4
5.5
(t
t
1
PCLK
PCLK
× 4
× 4) ÷ 2 – 1
Max
9.9
Unit
ns
ns
ns
ns
ns
ns