XC5VLX30-1FFG676C Xilinx Inc, XC5VLX30-1FFG676C Datasheet - Page 52

• Manufacturer Part Number: XC5VLX30-1FFG676C
• Description: IC FPGA VIRTEX-5 30K 676FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX30-1FFG676C

• Total Ram Bits: 1179648
• Number Of Logic Elements/cells: 30720
• Number Of Labs/clbs: 2400
• Number Of I /o: 400
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 676-BBGA, FCBGA
• No. Of Logic Blocks: 4800
• No. Of Gates: 30000
• Family Type: Virtex-5 LX
• No. Of Speed Grades: 1
• No. Of I/o's: 400
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1559

Table 70: Configuration Switching Characteristics (Cont’d)
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
BPI Master Flash Mode Programming Switching
T
T
T
SPI Master Flash Mode Programming Switching
T
T
T
T
CCLK Output (Master Modes)
T
T
CCLK Input (Slave Modes)
T
T
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
F
T
T
T
T
T
T
BPICCO
BPIDCC
INITADDR
SPIDCC
SPICCM
SPICCFC
FSINIT
MCCKL
MCCKH
SCCKL
SCCKH
DCK
DMCCK_DADDR
DMCCK_DI
DMCCK_DEN
DMCCK_DWE
DMCKO_DO
DMCKO_DRDY
Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
To support longer delays in configuration, use the design solutions described in UG190: Virtex-5 FPGA User Guide
DO will hold until next DRP operation.
Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
/T
/T
/T
(4)
FSINITH
BPICCD
SPIDCCD
/T
DMCKC_DI
/T
/T
Symbol
DMCKC_DEN
DMCKC_DWE
/T
DMCKC_DADDR
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
FWE_B outputs valid after CCLK rising edge
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address
cycles
DIN Setup/Hold before/after the rising CCLK
edge
MOSI clock to out
FCS_B clock to out
FS[2:0] to INIT_B rising edge Setup and Hold
Master CCLK clock minimum Low time
Master CCLK clock minimum High time
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
Maximum frequency for DCLK
DADDR Setup/Hold
DI Setup/Hold
DEN Setup/Hold time
DWE Setup/Hold time
CLK to out of DO
CLK to out of DRDY
Description
(3)
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
500
3.0
0.5
3.0
4.0
0.0
3.0
3.0
2.0
2.0
1.2
0.0
1.2
0.0
1.2
0.0
1.2
0.0
1.0
1.0
10
10
10
-3
2
Speed Grade
1.35
1.35
1.35
1.35
1.12
1.12
450
3.0
0.5
3.0
4.0
0.0
3.0
3.0
2.0
2.0
0.0
0.0
0.0
0.0
10
10
10
-2
2
1.56
1.56
1.56
1.56
400
3.0
0.5
3.0
4.0
0.0
3.0
3.0
2.0
2.0
0.0
0.0
0.0
0.0
1.3
1.3
10
10
10
-1
.
2
CCLK cycles
ns, Min
ns, Min
ns, Min
ns, Min
Units
MHz
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
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