AT40K40AL-1BQU Atmel, AT40K40AL-1BQU Datasheet
AT40K40AL-1BQU
Specifications of AT40K40AL-1BQU
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AT40K40AL-1BQU Summary of contents
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... Easy Migration to Atmel Gate Arrays for High Volume Production • Supply Voltage 3.3V • 5V I/O Tolerant • Green (Pb/Halide-free/RoHS Compliant) Package Options Available ® ® ® , OrCAD , Synopsys , Verilog , Viewlogic 5K - 50K Gates Coprocessor FPGA with FreeRAM AT40K05AL AT40K10AL AT40K20AL AT40K40AL ® , 2818F–FPGA–07/06 ™ 1 ...
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... FPGAs. AT40K10AL AT40K20AL 10K - 20K 20K - 30K 576 1,024 (1) (1) 954 1,520 4,608 8,192 192 256 AT40K40AL 40K - 50K 2,304 (1) 3,048 18,432 384 2818F–FPGA–07/06 ...
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... AT40KAL series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’ ...
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... Array AT40KAL Series FPGA 4 At the heart of the Atmel architecture is a symmetrical array of identical cells, see Figure 1. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells, see Figure 2 on page 5. At the intersection of each repeater row and column there RAM block accessible by adjacent buses ...
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Figure 2. Floor Plan (Representative Portion) RAM RAM RAM RAM RAM ...
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The Busing Network AT40KAL Series FPGA 6 Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are ...
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Figure 3. Busing Plane (One of Five) = AT40KAL Core Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater Express Bus Local Bus AT40KAL Series FPGA Express Bus 7 ...
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Cell Connections The Cell AT40KAL Series FPGA 8 Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five ...
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Figure 5. The Cell "1" N "1" "1" 8X1 LUT 8X1 LUT OUT "0" "1" CLOCK RESET/SET Diagonal Direct Connect ...
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Figure 6. Some Single Cell Modes CARRY AT40KAL Series FPGA 10 Synthesis Mode. This mode is ...
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RAM 2818F–FPGA–07/ dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects ...
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... RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the “AT40K/40KAL Configura- tion Series” application note at www.atmel.com). Figure 8. RAM Logic CLOCK “ ...
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Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) AT40KAL Series FPGA 13 ...
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Clocking Scheme AT40KAL Series FPGA 14 There are eight Global Clock buses (GCK1 - GCK8) on the AT40KAL FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used ...
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Figure 10. Clocking (for One Column of Cells) Express Bus (Plane 4; Half Length at Edge) Repeater AT40KAL Series FPGA } FCK (2 per Edge Column of the Array) ⎫ ⎬ GCK1 - GCK8 ⎭ Column Clock Mux “1” ...
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Set/Reset Scheme AT40KAL Series FPGA 16 The AT40KAL family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except ...
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Figure 11. Set/Reset (for One Column of Cells) Repeater Express Bus (Plane 5; Half Length at Edge) Any User I/O can Drive Global Set/Reset Lone AT40KAL Series FPGA Each Cell has a Programmable Set or Reset Sector Set/Reset Mux ...
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I/O Structure PAD PULL-UP/PULL-DOWN CMOS SCHMITT DELAYS DRIVE TRI-STATE SOURCE SELECTION MUX AT40KAL Series FPGA 18 The AT40KAL has registered I/Os and group enable every sector for tri-states on obuf’s. The I/O pad is the one that connects the I/O ...
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Primary, Secondary and Corner I/Os Primary I/O Secondary I/O Corner I/O 2818F–FPGA–07/06 The AT40KAL has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KAL has access to one ...
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AT40KAL Series FPGA 20 Figure 12. West Primary I/O (Mirrored for East I/O) PULL-UP PAD PULL-DOWN Figure 13. West Secondary I/O (Mirrored for East I/O) PULL-UP PAD PULL-DOWN CELL "0" "1" "0" "1" CELL CELL "0" "1" CELL "0" "1" ...
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Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) VCC TRI-ST ATE RST PULL-UP PAD PULL-DOWN 2818F–FPGA–07/06 PAD GND TTL/CMOS DRIVE TRI-ST ATE SCHMITT DELAY ICLK OCLK RST RST "0" "1" "0" "1" AT40KAL Series FPGA PAD VCC GND TTL/CMOS DRIVE ...
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Absolute Maximum Ratings – 3.3V Commercial/Industrial* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .................................-0. Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering Temp. ...
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DC Characteristics – 3.3V Operation Commercial/Industrial Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level Tri-state ...
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... AT40K05AL Maximum Current Supply AT40K10AL AT40K20AL Maximum Current Supply AT40K40AL Notes: 1. This specification applies to Commercial and Industrial grade products only. 2. Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A larger capacity power supply may result in a larger initialization current. ...
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AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Cell ...
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AC Timing Characteristics – 3.3V Operation Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t All ...
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... GSRN AT40K20AL pad -> GSRN AT40K40AL clock pad -> out AT40K05AL clock pad -> out AT40K10AL clock pad -> out AT40K20AL clock pad -> out AT40K40AL clock pad -> out AT40K05AL clock pad -> out AT40K10AL clock pad -> out AT40K20AL clock pad -> out AT40K40AL AT40KAL Series FPGA of 50 ...
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... OXZ Notes: 1. CMOS buffer delays are measured from Buffer delay pad voltage of 1.5V with one output switching. 3. Parameter based on characterization and simulation; not tested in production. 4. Exact power calculation is available in Atmel FPGA Designer software. AT40KAL Series FPGA 28 = 3.0V, temperature = 70° 3.6V, temperature = 0°C ...
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FreeRAM Asynchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read 2818F–FPGA–07/ AWS 0 ADDR OXZ DS DATA WE t AWS 0 WR ADDR PREV. WR DATA RD ADDR = WR ADDR 1 t ...
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FreeRAM Synchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read AT40KAL Series FPGA 30 CLK t WCS WE t ACS 0 ADDR OE t OXZ t DCS DATA CLK ADDR t WR DATA ...
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... I/O6 I/O6 (A19) (A19) I/O7 I/O7 I/O8 I/O8 I/O9 I/O10 I/O11 I/O12 GND GND Note: 1. On-chip tri-state 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC GND GND I/O1, I/O1, GCK1 GCK1 (A16) (A16) I/O2 I/O2 (A17) (A17) I/O3 I/O3 ...
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... I/O13 I/O21 I/O14 I/O22 I/O15 I/O23 (A22) (A22) I/O16 I/O24 (A23) (A23) GND GND VCC VCC Note: 1. On-chip tri-state AT40KAL Series FPGA 32 AT40K40AL 84 256 I/O 384 I/O PLCC I/O17, I/O25, FCK1 FCK1 I/O18 I/O26 I/O19 I/O27 17 (A20) (A20) I/O20 I/O28 18 (A21) ...
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... VCC I/O21 I/O33 I/O22 I/O34 I/O23 I/O35 I/O24, I/O36, FCK2 FCK2 GND GND I/O37 Note: 1. On-chip tri-state 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC I/O33 I/O49 I/O34 I/O50 I/O51 I/O52 I/O35 I/O53 I/O36 I/O54 GND I/O37 I/O55 I/O38 ...
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... I/O31 I/O47 (1) (1) (OTS) (OTS) I/O32, I/O48, GCK2 GCK2 M1 M1 GND GND M0 M0 Note: 1. On-chip tri-state AT40KAL Series FPGA 34 AT40K40AL 84 256 I/O 384 I/O PLCC I/O52 I/O76 I/O77 I/O78 GND I/O79 I/O80 I/O53 I/O81 I/O54 I/O82 I/O55 I/O83 I/O56 I/O84 GND ...
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... I/O53 I/O38 I/O54 (LDC) (LDC) I/O39 I/O55 I/O40 I/O56 I/O57 I/O58 I/O59 I/O60 GND GND I/O41 I/O61 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC VCC VCC M2 M2 I/O65, I/O97, GCK3 GCK3 I/O66 I/O98 (HDC) (HDC) I/O67 I/O99 I/O68 ...
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... I/O48 I/O72 (INIT) (INIT) VCC VCC GND GND I/O49 I/O73 (D14) (D14) I/O50 I/O74 (D13) (D13) AT40KAL Series FPGA 36 AT40K40AL 84 256 I/O 384 I/O PLCC I/O82 I/O122 I/O83 I/O123 38 I/O84 I/O124 39 VCC VCC I/O85 I/O125 I/O86 I/O126 GND I/O127 ...
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... I/O53 I/O81 (D12) (D12) I/O54 I/O82 (D11) (D11) I/O55 I/O83 I/O56 I/O84 GND GND I/O85 I/O86 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC I/O147 I/O148 I/O149 I/O150 GND I/O99 I/O151 I/O100 I/O152 I/O101 I/O153 I/O102 I/O154 I/O103 I/O155 ...
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... I/O61 I/O93 I/O62 I/O94 I/O63 I/O95 (D8) (D8) I/O64, I/O96, GCK4 GCK4 GND GND CON CON AT40KAL Series FPGA 38 AT40K40AL 84 256 I/O 384 I/O PLCC I/O174 GND I/O175 I/O176 I/O117 I/O177 I/O118 I/O178 I/O119 I/O179 I/O120 I/O180 GND GND VCC VCC ...
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... I/O102 I/O69 I/O103 (D6) (D6) I/O70 I/O104 I/O71 I/O105 I/O72 I/O106 I/O107 I/O108 GND GND I/O109 I/O110 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC VCC VCC RESET RESET I/O129 I/O193 (D7) (D7) I/O130, I/O194, GCK5 GCK5 I/O131 I/O195 I/O132 I/O196 ...
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... I/O117 I/O78 I/O118 I/O79(D4) I/O119(D4) I/O80 I/O120 VCC VCC GND GND I/O81 I/O121 (D3) (D3) I/O82 I/O122 (CHECK) (CHECK) AT40KAL Series FPGA 40 AT40K40AL 84 256 I/O 384 I/O PLCC I/O147, I/O219, FCK3 FCK3 I/O148 I/O220 VCC VCC I/O149 I/O221 59 (D5) (D5) I/O150 I/O222 60 (CS0) ...
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... I/O86 I/O128 VCC I/O87 I/O129 I/O88, I/O130, FCK4 FCK4 I/O131 I/O132 GND GND I/O133 I/O134 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC I/O243 I/O244 I/O163 I/O245 I/O164 I/O246 GND I/O165 I/O247 I/O166 I/O248 I/O167 I/O249 I/O168 I/O250 ...
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... I/O94 I/O142 I/O95 I/O143 (D0) (D0) I/O96, I/O144, GCK6 GCK6 (CSOUT) (CSOUT) CCLK CCLK VCC VCC TSTCLK TSTCLK AT40KAL Series FPGA 42 AT40K40AL 84 256 I/O 384 I/O PLCC I/O270 GND I/O181 I/O271 I/O182 I/O272 I/O183 I/O273 I/O184 I/O274 I/O275 I/O276 GND GND VCC ...
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... I/O150 (A3) (A3) (1) I/O151 I/O152 I/O103 I/O153 (1) I/O104 I/O154 I/O155 I/O156 GND GND Note: 1. Shared with TSTCLK. No Connect. 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC GND GND I/O193 I/O289 (A0) (A0) I/O194, I/O290, GCK7 GCK7 (A1) (A1) I/O195 I/O291 I/O196 I/O292 ...
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... I/O165 I/O110 I/O166 I/O111 I/O167 (A6) (A6) I/O112 I/O168 (A7) (A7) GND GND VCC VCC Note: 1. Shared with TSTCLK. No Connect. AT40KAL Series FPGA 44 AT40K40AL 84 256 I/O 384 I/O PLCC I/O209 I/O313 I/O210 I/O314 I/O211 I/O315 I/O212 I/O316 VCC VCC I/O213 I/O317 I/O214 I/O318 ...
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... I/O118 I/O176 (A11) (A11) VCC I/O177 I/O178 I/O119 I/O179 I/O120 I/O180 GND GND Note: 1. Shared with TSTCLK. No Connect. 2818F–FPGA–07/06 AT40K20AL AT40K40AL 256 I/O 384 I/O PLCC I/O225 I/O337 (A8) (A8) I/O226 I/O338 (A9) (A9) I/O339 I/O340 I/O341 I/O342 GND I/O227 ...
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... I/O126 I/O190 I/O127 I/O191 (A14) (A14) I/O128, I/O192, GCK8 GCK8 (A15) (A15) VCC VCC Note: 1. Shared with TSTCLK. No Connect. AT40KAL Series FPGA 46 AT40K40AL 84 256 I/O 384 I/O PLCC I/O242 I/O362 I/O243 I/O363 I/O244 I/O364 I/O365 I/O366 GND I/O367 I/O368 I/O245 I/O369 ...
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... Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 208Q1 208-lead, Plastic Quad Flat Package (PQFP) 240Q1 240-lead, Plastic Quad Flat Package (PQFP) 2818F–FPGA–07/06 AT40K10AL 114 114 128 161 – – Package Type AT40KAL Series FPGA AT40K20AL AT40K40AL – – 114 114 161 161 – 193 47 ...
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... AT40K20AL-1BQI AT40K20AL-1DQI Speed Grade (ns) Ordering Code AT40K40AL-1BQC 1 AT40K40AL-1DQC AT40K40AL-1EQC AT40K40AL-1BQI 1 AT40K40AL-1DQI AT40K40AL-1EQI Speed Grade (ns) Ordering Code AT40K05AL-1BQU AT40K10AL-1BQU 1 AT40K20AL-1BQU AT40K40AL-1BQU (1) Package Operation Range 84J 100T1 Commercial 144L1 (0°C to 70°C) 208Q1 84J 100T1 Industrial 144L1 (-40°C to 85°C) 208Q1 (1) Package Operation Range ...
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Packaging Information 84J – PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) ...
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TQFP Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body ...
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LQFP Top View Side View 1. This drawing is for general information only; refer to JEDEC Drawing MS-026 for additional information. Notes: 2. The top package body size may be smaller than ...
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PQFP e Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom ...
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PQFP D1 E1 Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-029, Variation GA, for additional information. 2. All dimensioning and tolerancing conforms to ASME Y14.5M-1994. ...
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Revision History Revision Level – Release Date History F – July 2006 Added Green (Pb/Halide-free/RoHS Compliant) 144-lead LQFP. AT40KAL Series FPGA 54 2818F–FPGA–07/06 ...
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