XC3S100E-4TQG144I Xilinx Inc, XC3S100E-4TQG144I Datasheet
XC3S100E-4TQG144I
Specifications of XC3S100E-4TQG144I
Available stocks
Related parts for XC3S100E-4TQG144I
XC3S100E-4TQG144I Summary of contents
Page 1
R DS312 March 21, 2005 Module 1: Introduction and Ordering Information DS312-1 (v1.1) March 21, 2005 6 pages • Introduction • Features • Architectural Overview • Package Marking • Ordering Information Module 2: Functional Description DS312-2 (v1.1) March 21, 2005 ...
Page 2
... Multi-voltage, multi-standard SelectIO™ interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards Table 1: Summary of Spartan-3E FPGA Attributes Equivalent System Logic Device Gates Cells Rows Columns XC3S100E 100K 2,160 22 XC3S250E 250K 5,508 34 XC3S500E 500K 10,476 46 XC3S1200E 1200K ...
Page 3
... Notes: 1. The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom. 2 • Digital Clock Manager (DCM) Blocks provide ...
Page 4
... Slave Serial, typically downloaded from a processor • Slave Parallel, typically downloaded from a processor • Boundary Scan (JTAG), typically downloaded from a processor or system tester. Table 2: Available User I/Os and Differential (Diff) I/O Pairs VQ100 CP132 VQG100 CPG132 Device User Diff User XC3S100E XC3S250E XC3S500E - - 92 XC3S1200E - - ...
Page 5
Introduction and Ordering Information Package Marking Figure 2 provides a top marking example for Spartan-3E FPGAs in the quad-flat packages. marking for Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA ...
Page 6
... Speed Grade Package Type Pb-Free Packaging Example: XC3S250E -4 FT Device Type Speed Grade Package Type Device Speed Grade XC3S100E –4 Standard Performance XC3S250E –5 High Performance XC3S500E XC3S1200E XC3S1600E Notes: 1. The –5 speed grade is exclusively available in the Commercial temperature range. DS312-1 (v1.1) March 21, 2005 ...
Page 7
Introduction and Ordering Information Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. 03/21/05 1.1 Added XC3S250E in CP132 package to for CP132 package. Added package markings for QFP packages ...
Page 8
R DS312-2 (v1.1) March 21, 2005 Introduction As described in Architectural Overview, the Spartan™-3E FPGA architecture consists of five fundamental functional elements: • Input/Output Blocks (IOBs) • Configurable Logic Block (CLB) and Slice Resources • Block RAM • Dedicated Multipliers ...
Page 9
Functional Description T T1 TCE T2 ODDROUT1 O1 ODDRIN1 OTCLK1 OCE O2 ODDRIN2 OTCLK2 ODDROUT2 I IQ1 IDDRIN1 IDDRIN2 ICLK1 ICE IQ2 ICLK2 SR REV Notes: 1. All IOB signals communicating with the FPGA’s internal logic have the option of ...
Page 10
R Input Delay Functions Each IOB has a programmable delay block that can delay the input signal from 0 to nominally 4000 ps. In signal is first delayed by either 0 or 2000 ps (nominal) and is then applied to ...
Page 11
Functional Description Storage Element Functions There are three pairs of storage elements in each IOB, one pair for each of the three paths possible to configure each of these storage elements as an edge-triggered D-type flip-flop (FD) or ...
Page 12
R Table 2: Storage Element Options Option Switch SRHIGH/SRLOW Determines whether SR acts as a Set, which forces the storage element to a logic "1" (SRHIGH Reset, which forces a logic "0" (SRLOW) INIT1/INIT0 When Global Set/Reset (GSR) ...
Page 13
Functional Description Register Cascade Feature In the Spartan-3E family, one of the IOBs in a differential pair can cascade either its input or output storage elements with those in the other IOB of the differential pair. This is intended to ...
Page 14
From Fabric D2 D OCLK1 OCLK2 OCLK1 OCLK2 D1 d d+2 d+4 D2 d+1 d+3 d+5 PAD d d+1 d+2 d+3 d+4 Figure 6: Output DDR (without Cascade Feature) DS312-2 (v1.1) March 21, 2005 Advance Product Specification ...
Page 15
Functional Description Table 3: Single-Ended IOSTANDARD Bank Compatibility Single-Ended 1.2 V 1.5 V IOSTANDARD LVTTL - - LVCMOS33 - - LVCMOS25 - - LVCMOS18 - - Input/ LVCMOS15 - Output Input/ LVCMOS12 Input Output PCI33_3 - - PCI66_3 - - ...
Page 16
R Table 4: Differential IOSTANDARD Bank Compatibility Differential IOSTANDARD On-chip Differential Termination, LVDS_25 On-chip Differential Termination, RSDS_25 MINI_LVDS_25 On-chip Differential Termination, LVPECL_25 On-chip Differential Termination BLVDS_25 On-chip Differential Termination, Notes: 1. Each bank can support any two of the following: ...
Page 17
Functional Description pull-down resistors are commonly applied to unused I/Os, inputs, and three-state outputs, but can be used on any I/O. The pull-up resistor connects an I resistor. The resistance value depends on the V (see Module 3 ...
Page 18
R Bank 0 Bank 2 DS312-2_26_021205 Figure 10: Spartan-3E I/O Banks (top view) I/O Banking Rules When assigning I/Os to banks, these V followed: 1. All V pins on the FPGA must be connected even if a CCO bank is ...
Page 19
Functional Description levels (see Table 2 of Module 3). At this time, all I/O drivers are in a high-impedance state. V CCO V serve as inputs to the internal Power-On Reset cir- CCAUX cuit (POR). A Low level applied to ...
Page 20
... The LUTs can be used as a 16x1 memory (RAM16 16-bit shift register (SRL16), Spartan-3E FPGA Table 6: Spartan-3E CLB Resources CLB CLB Device Rows Columns XC3S100E 22 16 XC3S250E 34 26 XC3S500E 46 34 XC3S1200E 60 ...
Page 21
Functional Description . Notes: 1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. The index i can depending on the slice. The upper ...
Page 22
R Switch Matrix SHIFTOUT Slice Location Designations The Xilinx development software designates the location of a slice according to its X and Y coordinates, starting in the bottom left corner, as shown in Figure lowed by a number identifies columns ...
Page 23
Functional Description The SLICEM pair supports two additional functions: • Two 16x1 distributed RAM blocks, RAM16 • Two 16-bit shift registers, SRL16 Each of these elements is described in more detail in the fol- lowing sections. Logic Cells The combination ...
Page 24
R Table 7: Slice Inputs and Outputs (Continued) Name Location CLK SLICEL/M Common SHIFTIN SLICEM Top SHIFTOUT SLICEM Bottom CIN SLICEL/M Bottom COUT SLICEL/M Top X SLICEL/M Bottom Y SLICEL/M Top XB SLICEL/M Bottom YB SLICEL/M Top XQ SLICEL/M Bottom ...
Page 25
Functional Description ing LUTs or by using the wide function multiplexers that are described later. The output of the LUT can connect to the wide multiplexer logic, the carry and arithmetic logic, or directly to a CLB out- put or ...
Page 26
R FXINB FXINA FXINB FXINA FXINB F7 FXINA F5 FXINB F6 FXINA F5 Figure 17: Muxes and Dedicated Feedback in Spartan-3E CLB Table 8: Mux Capabilities Mux Usage F5MUX F5MUX FiMUX F6MUX F7MUX F8MUX DS312-2 (v1.1) March 21, 2005 Advance ...
Page 27
Functional Description The wide multiplexers can be used by the automatic tools or instantiated in a design using a component such as the F5MUX. The symbol, signals, and function are described below. The description is similar for the F6MUX, F7MUX, ...
Page 28
R G[4: F[4: Table 11: Carry Logic Functions Function CYINIT Initializes carry chain for a slice. Fixed selection of: • CIN carry input from the slice below • BX input CY0F Carry generation for bottom ...
Page 29
Functional Description Table 11: Carry Logic Functions (Continued) Function CYMUXG Carry generation or propagation mux for top half of slice. Dynamic selection via CYSELF of: • CYMUXF carry propagation (CYSELG = 1) • CY0G carry generation (CYSELG = 0) CYSELF ...
Page 30
R The MULT_AND is useful for small multipliers. Larger multi- pliers can be built using the dedicated 18x18 multiplier blocks (see Dedicated Multipliers). Storage Elements The storage element, which is programmable as either a D-type flip-flop or a level-sensitive transparent ...
Page 31
Functional Description Initialization The CLB storage elements are initialized at power-up, dur- ing configuration, by the global GSR signal, and by the indi- vidual SR or REV inputs to the CLB. Table 14: Slice Storage Element Initialization Signal Description SR ...
Page 32
R RAM16X1D WE D WCLK DPRA0 DPRA1 DPRA2 DPRA3 DS312-2_42_021305 Figure 24: Dual-Port RAM Component Table 15: Dual-Port RAM Function Inputs WE (mode) WCLK D 0 (read (read (read) 1 ...
Page 33
Functional Description SRLC16 SHIFTIN SHIFT-REG 4 D A[3:0] A[3:0] MC15 (BY) WSG CE (SR) WE CLK CK SHIFTOUT or YB Figure 25: Logic Cell SRL16 Structure Each shift register provides a shift output MC15 for the last ...
Page 34
... Arrangement of RAM Blocks on Die The block RAMs are located together with the multipliers on the die in one or two columns depending on the size of the device. The XC3S100E has one column of block RAM. The Spartan-3E devices ranging from the XC3S250E to XC3S1600E have two columns of block RAM. ...
Page 35
Functional Description Table 19: Port Aspect Ratios DIP/DOP Total Data DI/DO Data Parity Bus Path Width Bus Width Width 1 (w bits) (w-p bits) (p bits Notes: 1. ...
Page 36
R Parity 512x36 Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B Block RAM Port Signal Definitions Representations of the RAMB16_S[w ]_S[w ] and ...
Page 37
Functional Description RAMB16_w WEA ENA SSRA CLKA ADDRA[r –1:0] A DIA[w –p –1: DIPA[p –1:0] A WEB ENB SSRB CLKB ADDRB[r –1:0] B DIB[w –p –1: DIPB[p –1:0] B (a) Dual-Port Notes and w ...
Page 38
R Table 20: Block RAM Port Signals (Continued) Port A Port B Signal Signal Signal Description Name Name Data Output Bus DOA Parity Data DOPA DOPB Output(s) Write Enable WEA Clock Enable ENA Set/Reset SSRA SSRB Clock CLKA CLKB Block ...
Page 39
Functional Description Table 21: Block RAM Attributes (Continued) Function Data Output Latch Synchronous Set/Reset Value Data Output Latch Behavior during Write (see Block RAM Data Operations) Block RAM Data Operations Writing data to and accessing data from the block RAM ...
Page 40
R There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by ...
Page 41
Functional Description Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 31: Waveforms of Block RAM Data Operations with READ_FIRST Selected Data_in CLK WE DI ADDR DO 0000 EN DISABLED Figure 32: Waveforms of Block RAM Data Operations with ...
Page 42
R Dedicated Multipliers The Spartan-3E devices provide dedicated multiplier blocks per device. The multipliers are located together with the block RAM in one or two columns depending on device density. See Arrangement of RAM Blocks on Die ...
Page 43
Functional Description MULT18X18SIO A[17:0] B[17:0] CEA CEB CEP CLK RSTA RSTB RSTP BCIN[17:0] Figure 34: MULT18X18SIO Primitive CEB CLK RSTB BCIN[17:0] CEB B[17:0] CLK RSTB 36 The MULT18X18SIO primitive has two additional ports called BCIN and BCOUT to cascade or ...
Page 44
... BCOUT port of the top-most block in a column example, Figure 36 shows the multiplier cas- cade capability within the XC3S100E FPGA, which has a single column of multiplier, four blocks tall. For clarity, the figure omits the register control inputs. DS312-2 (v1.1) March 21, 2005 ...
Page 45
Functional Description Table 24 defines each port of the MULT18X18SIO primitive. Table 24: MULT18X18SIO Embedded Multiplier Primitives Description Signal Name Direction A[17:0] Input B[17:0] Input BCIN[17:0] Input P[35:0] Output BCOUT[17:0] Output CEA Input RSTA Input CEB Input RSTB Input CEP ...
Page 46
... DCM. See XAPP462: "Using Digital Clock Managers (DCMs) in Spartan-3 Series FPGAs" for further information. The XC3S100E FPGA has two DCMs, one at the top and one at the bottom of the device. The XC3S250E and XC3S500E FPGAs each include four DCMs, two at the top and two at the bottom ...
Page 47
Functional Description CLKIN CLKFB RST Table 25: DLL Signals Signal Direction CLKIN Input CLKFB Input CLK0 Output CLK90 Output CLK180 Output CLK270 Output CLK2X Output CLK2X180 Output CLKDV Output Delay-Locked Loop (DLL) The most basic function of the DLL component ...
Page 48
R This phase error is a measure of the clock skew that the clock distribution network introduces. The control block acti- vates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the ...
Page 49
Functional Description FPGA CLK90 BUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 CLK0 (a) On-Chip with CLK0 Feedback FPGA CLK90 IBUFG CLK180 CLKIN CLK270 CLKDV DCM CLK2X CLK2X180 CLKFB CLK0 IBUFG CLK0 (c) Off-Chip with CLK0 Feedback Figure ...
Page 50
R ious values as described in Table 26. The basic frequency synthesis outputs are described in Table Duty Cycle Correction of DLL Clock Outputs (1) The CLK2X , CLK2X180, and CLKDV ordinarily exhibit a 50% duty cycle – even if ...
Page 51
Functional Description generating a clock with the new target frequency on the CLKFX and CLKFX180 outputs. Though classified as belonging to the DLL component, the CLKIN input is shared with the DFS component. This case does not employ feed- back ...
Page 52
R ponent is enabled by setting the attribute to either the FIXED or VARIABLE values, which select the Fixed Phase Table 29: PS Attributes Attribute CLKOUT_PHASE_SHIFT Disables the PS component or chooses between Fixed Phase and Variable Phase modes. PHASE_SHIFT ...
Page 53
Functional Description a. CLKOUT_PHASE_SHIFT = NONE b. CLKOUT_PHASE_SHIFT = FIXED Shift Range over all P Values: c. CLKOUT_PHASE_SHIFT = VARIABLE Shift Range over all P Values: Shift Range over all N Values: The Variable Phase Mode The Variable Phase mode ...
Page 54
R Just following device configuration, the PS component ini- tially determines T by evaluating Equation (4) for the PS value assigned to the PHASE_SHIFT attribute. Then to dynamically adjust that phase shift, use the three PS inputs to increase or ...
Page 55
Functional Description Stabilizing DCM Clocks Before User Mode The STARTUP_WAIT attribute shown in delays the end of the FPGA’s configuration process until after the DCM locks to the incoming clock frequency. This option ensures that the FPGA remains in the ...
Page 56
... Number of DCMs and locations of these DCM varies for different device densities. 2. The left and right DCMs are only in the XC3S1200E and XC3S1600E. The XC3S100E has only two DCMs, one on the top right and one on the bottom right of the die. Figure 42: Spartan-3E Internal Quadrant-Based Clock Network (Top View) DS312-2 (v1 ...
Page 57
... LHCLK1 H X0Y9 LHCLK0 Notes: 1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks. 2. See Figure 42 for specific BUFGMUX locations and within a quadrant. 50 XC3S100E XC3S250E/XC3S500E DCM_X0Y0 DCM_X1Y0 N/A N/A N/A N/A DCM_X0Y1 DCM_X1Y1 N/A DCM_X0Y1 N/A N/A N/A N/A ...
Page 58
R CLK Switch LHCLK or RHCLK input Double Line DCM output* *(XC3S1200E and and XC3S1600E only) Figure 43: Clock Switch Matrix to BUFGMUX Pair Connectivity Quadrant Clock Routing The clock routing within the FPGA is quadrant-based, as shown in Figure ...
Page 59
Functional Description BUFGMUX Output X2Y1 (Global) X0Y2 (Left Half) X2Y0 (Global) X0Y3 (Left Half) X1Y1 (Global) X0Y4 (Left Half) X1Y0 (Global) X0Y5 (Left Half) X2Y11 (Global) X0Y6 (Left Half) X2Y10 (Global) X0Y7 (Left Half) X1Y11 (Global) X0Y8 (Left Half) X1Y10 ...
Page 60
R Interconnect Interconnect is the programmable network of signal path- ways between the inputs and outputs of functional elements within the FPGA, such as IOBs, CLBs, DCMs, block RAM, etc. Interconnect, also called routing, is segmented for optimal connectivity. Functionally, ...
Page 61
Functional Description There are four type of general-purpose interconnect avail- able in each channel, as shown in Figure 47 below. Long Lines Each set of 24 long line signals spans the die both horizon- tally and vertically and connects to ...
Page 62
R Horizontal and Vertical Double Lines (horizontal channel shown as an example) Direct Connections Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles DS312-2 (v1.1) March 21, 2005 Advance Product Specification 8 CLB CLB CLB DS312-2_15_022305 CLB CLB CLB CLB ...
Page 63
Functional Description Configuration Differences from Spartan-3 FPGAs In general, Spartan-3E FPGA configuration modes are a superset to those available in Spartan-3 FPGAs. Two new modes added in Spartan-3E FPGAs provide a glue-less configuration interface to industry-standard parallel NOR Flash and ...
Page 64
... Table 39. The configuration file size for a multiple-FPGA daisy-chain design equals the sum of the individual file sizes. Table 39: Number of Bits to Program a Spartan-3E FPGA (Uncompressed Bitstreams) Number of Configuration Device XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Table 40: Pin Behavior during Configuration Master SPI (Serial Pin Name ...
Page 65
Functional Description Table 40: Pin Behavior during Configuration (Continued) Master SPI (Serial Pin Name Serial D0/DIN DIN RDWR_B A23 A22 A21 A20 A19/VS2 A18/VS1 A17/VS0 A16 A15 A14 A13 A12 A11 A10 ...
Page 66
R Table 41 shows the default I/O standard setting for the vari- ous configuration pins during the configuration process. The configuration interface is designed primarily for 2.5V opera- tion when the VCCO_2 (and VCCO_1 in BPI mode) con- nects to ...
Page 67
Functional Description The mode select pins, M[2:0], must all be Low when sam- pled, when the FPGA’s INIT_B output goes High. After con- figuration, when the FPGA’s DONE output goes High, the mode select pins are available as full-featured user-I/O ...
Page 68
... Platform Flash PROM large enough to contain the sum of the various FPGA file sizes. Table 43: Number of Bits to Program a Spartan-3E FPGA and Smallest Platform Flash PROM Number of Configuration Device Bits XC3S100E 581,344 XC3S250E 1,352,192 XC3S500E 2,267,136 XC3S1200E 3,832,320 XC3S1600E 5,957,760 DS312-2 (v1 ...
Page 69
Functional Description +1.2V VCCINT P HSWAP VCCO_0 VCCO_2 DIN Serial Master Mode CCLK ‘0’ M2 DOUT ‘0’ M1 INIT_B ‘0’ M0 Spartan-3E FPGA +2.5V JTAG VCCAUX TDI TDI TDO TMS TMS TCK TCK TDO PROG_B DONE GND PROG_B Recommend open-drain ...
Page 70
R P SPI Mode ‘0’ ‘0’ ‘1’ Variant Select ‘1’ S ‘1’ +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 50: SPI Flash PROM Interface for PROMs Supporting READ (0x03) and FAST_READ (0x0B) S Although SPI is ...
Page 71
Functional Description +1.2V VCCINT P HSWAP SPI Mode ‘0’ M2 ‘0’ M1 ‘1’ M0 Variant Select Spartan-3E FPGA ‘1’ VS2 ‘1’ VS1 ‘0’ VS0 +2.5V JTAG TDI TDI TMS TMS TCK TCK TDO PROG_B PROG_B Recommend open-drain driver Figure 51: ...
Page 72
R Table 45: Variant Select Codes for SPI Serial Flash PROMs SPI Read VS2 VS1 VS0 Command FAST READ (0x0B (see Figure 50) READ (0x03 (see Figure 50) READ ARRAY (0xE8) ...
Page 73
Functional Description Table 46: SPI Flash PROM Connections and Pin Naming (Continued) SPI Flash Pin FPGA Connection Only applicable to Atmel DataFlash. Not required for FPGA configuration but must be High during configuration. Optional RESET connection to FPGA user I/O ...
Page 74
R Table 47: Serial Peripheral Interface (SPI) Connections (Continued) Pin Name FPGA Direction Output Chip Select Output. Active Low. CSO_B Output Configuration Clock. Generated CCLK by FPGA internal oscillator. Frequency controlled by ConfigRate bitstream generator option. If CCLK PCB trace ...
Page 75
Functional Description Power-On Precautions if 3.3V Supply is Last in Sequence Spartan-3E FPGAs have a built-in power-on reset (POR) circuit, as shown in Figure 63. The FPGA waits for its three — power supplies VCCINT, VCCAUX, and VCCO to I/O ...
Page 76
... PROM can also store application code for a MicroBlaze™ RISC processor core integrated in the Spartan-3E FPGA. See Using the SPI Flash Interface after Table 49: Number of Bits to Program a Spartan-3E FPGA and Smallest SPI Flash PROM Number of Configuration Device Bits XC3S100E 581,344 XC3S250E 1,352,192 XC3S500E 2,267,136 XC3S1200E 3,832,320 XC3S1600E 5,957,760 CCLK Frequency In SPI Flash mode, the FPGA’ ...
Page 77
Functional Description Spartan-3E FPGA FPGA-based SPI Master Figure 53: Using the SPI Flash Interface After Configuration Similarly, the SPI bus can be expanded to additional SPI peripherals. Because SPI is a common industry-standard interface, there are a variety of SPI-based ...
Page 78
R +1.2V VCCINT P HSWAP VCCO_0 VCCO_2 SPI Mode ‘0’ M2 CSO_B ‘0’ M1 ‘1’ M0 Variant Select Spartan-3E ‘1’ VS2 FPGA S VS1 ‘1’ VS0 +2.5V VCCAUX JTAG TDI TDI TMS TMS TCK TCK TDO PROG_B GND PROG_B Recommend ...
Page 79
Functional Description Not available in VQ100 package BPI Mode +2.5V JTAG TDI TMS TCK TDO PROG_B Recommend open-drain driver Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs A During configuration, the value of the M0 ...
Page 80
R High, the HSWAP pin is available as full-featured user-I/O pin and is powered by the VCCO_0 supply. The RDWR_B and CSI_B must be Low throughout the con- figuration process. After configuration, these pins also become user I/ ...
Page 81
Functional Description Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued) Pin Name FPGA Direction A[23:0] Output Address D[7:0] Input Data Input CSO_B Output Chip Select Output. Active Low. BUSY Output Busy Indicator. Typically only used after configuration, if bitstream option ...
Page 82
... FPGA applications. Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM Uncompressed Device File Sizes (bits) XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E CCLK Frequency In BPI mode, the FPGA’s internal oscillator generates the configuration clock frequency that controls all the interface timing ...
Page 83
Functional Description at the ConfigRate frequency and internally serialized with an 8X clock frequency. Table 53: Maximum ConfigRate Settings for Parallel Flash PROMs Maximum ConfigRate Flash Read Access Time < 200 ns < Using the BPI Interface after ...
Page 84
R Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin Connection to Flash PROM with FPGA Pin IO15/A-1 Pin LDC2 BYTE# LDC1 OE# LDC0 CS# HDC WE# A[23:1] A[n:0] A0 IO15/A-1 D[7:0] IO[7:0] User I/O Upper data lines IO[14:8] ...
Page 85
Functional Description +1.2V VCCINT P HSWAP Not available in VQ100 package BPI Mode ‘0’ M2 ‘1’ Spartan-3E FPGA ‘0’ CSI_B ‘0’ RDWR_B 2.5V JTAG TDI TDI TMS TMS TCK TCK TDO PROG_B GND PROG_B Recommend open-drain driver ...
Page 86
R Parallel Flash PROM FFFFFF General FPGA Application User Area > 300 ns Diagnostics FPGA Application 0 First Configuration Figure 57: Use MultiBoot to Load Alternate Configuration Images Similarly, the general FPGA application could trigger a MultiBoot event at any ...
Page 87
Functional Description V Intelligent Download Host VCC Configuration Memory Source SELECT READ/WRITE • Internal memory CLOCK • Disk drive PROG_B • Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain driver ...
Page 88
R After configuration, all of the interface pins except DONE and PROG_B are available as user I/Os. Alternatively, the bidirectional SelectMAP configuration interface is available after configuration. To continue using SelectMAP mode, set the Persist bitstream generator option to Yes ...
Page 89
Functional Description Table 55: Slave Parallel Mode Connections (Continued) Pin Name FPGA Direction CSO_B Output Chip Select Output. Active Low. INIT_B Open-drain Initialization Indicator. Active Low. bidirectional I/O Goes Low at start of configuration during Initialization memory clearing process. Released ...
Page 90
R Parallel V Intelligent Download Host VCC DATA[7:0] Configuration BUSY Memory Source SELECT READ/WRITE • Internal memory CLOCK • Disk drive • PROG_B Over network • DONE Over RF link INIT_B GND • Microcontroller • Processor • Tester PROG_B Recommend ...
Page 91
Functional Description Intelligent V Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive INIT_B • Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain ...
Page 92
R Table 56: Slave Serial Mode Connections Pin Name FPGA Direction HSWAP Input User I/O Pull-Up Control. When Low during configuration, enables pull-up resistors in all I/O pins to respective I/O bank 0: Pull-up during configuration 1: No pull-ups M[2:0] ...
Page 93
Functional Description Intelligent V Download Host VCC Configuration CLOCK Memory Source SERIAL_OUT PROG_B • Internal memory DONE • Disk drive • INIT_B Over network • Over RF link GND • Microcontroller • Processor • Tester • Computer PROG_B Recommend open-drain ...
Page 94
R VCCINT P HSWAP JTAG Mode ‘1’ M2 Spartan-3E ‘0’ M1 ‘1’ M0 TDI TMS TCK PROG_B +2.5V JTAG TDI TMS TCK TDO Voltage Compatibility The 2.5V VCCAUX supply powers the JTAG interface. All of the user I/Os are separately ...
Page 95
Functional Description Figure 63: Generalized Spartan-3E FPGA Configuration Logic Block Diagram 88 www.xilinx.com R DS312-2_57_022405 DS312-2 (v1.1) March 21, 2005 Advance Product Specification ...
Page 96
R DS312-2 (v1.1) March 21, 2005 Advance Product Specification Set PROG_B Low Power-On after Power-On V >1V CCINT No and V > 2V CCAUX and V Bank 4 > 1V CCO Yes Yes Clear configuration PROG_B = Low memory No ...
Page 97
Functional Description Load JPROG instruction Figure 65: Boundary-Scan Configuration Flow Diagram 90 Set PROG_B Low Power-On after Power-On V >1V CCINT and V > CCAUX and V Bank 4 > 1V CCO Yes Clear Yes configuration PROG_B = ...
Page 98
R The FPGA signals when the memory-clearing phase is complete by releasing the open-drain INIT_B pin, allowing the pin to go High via the external pull-up resistor to VCCO_2. Loading Configuration Data Configuration data is then written to the FPGA’s ...
Page 99
Functional Description The relative timing of configuration events is programmed via the Bitstream Generator (BitGen) options in the Xilinx development software. For example, the GTS and GWE events can be programmed to wait for all the DONE pins to High ...
Page 100
R Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected ( default ) GWE_cycle All flip-flops LUT RAMs, and SRL16 shift registers, Block RAM, Configuration Startup GTS_cycle All I/O pins, 1, ...
Page 101
Functional Description Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued) Pins/Function Values Option Name Affected ( default ) Pullup TdoPin JTAG TDO pin Pulldown Pullnone TmsPin JTAG TMS pin Pullup Pulldown Pullnone UserID JTAG User ID register Security JTAG, ...
Page 102
R Powering Spartan-3E FPGAs Voltage Supplies Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple voltage supply inputs, as shown in supply inputs for internal logic functions, V Table 58: Spartan-3E Voltage Supplies Supply Input VCCINT Internal core supply voltage. Supplies all ...
Page 103
Functional Description Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. 03/21/05 1.1 Updated The Spartan-3E Family Data Sheet DS312-1, Spartan-3E FPGA Family: DS312-2, Spartan-3E FPGA Family: Functional Description (Module ...
Page 104
R DS312-3 (v1.0) March 1, 2005 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the ...
Page 105
DC and Switching Characteristics Table 2: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes and V supplies ...
Page 106
R Table 5: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description (2) I Leakage current at User I/O, L Dual-Purpose, and Dedicated pins (3) I Current through pull-up resistor at RPU User I/O, Dual-Purpose, and Dedicated ...
Page 107
... XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E supply current XC3S100E XC3S250E XC3S500E XC3S1200E XC3S1600E Table 4. Quiescent supply current is measured with all I/O drivers 2.5V. The FPGA is programmed with a "blank" configuration data file (i.e., a design CCAUX www.xilinx.com (4) Typ ...
Page 108
R Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) HSTL_I_18 1.7 HSTL_III_18 1.7 (4) LVCMOS12 1.1 (4) LVCMOS15 1.4 (4) LVCMOS18 1.65 (4,5) LVCMOS25 2.3 (4) LVCMOS33 ...
Page 109
DC and Switching Characteristics Table 8: DC Characteristics of User I/Os Using Single-Ended Standards IOSTANDARD Attribute HSTL_I_18 HSTL_III_18 (3) LVCMOS12 2 (3) LVCMOS15 (3) LVCMOS18 (3,4) LVCMOS25 (3) ...
Page 110
R Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) IOSTANDARD Attribute SSTL2_I Notes: 1. The numbers in this table are based on the conditions set forth in 2. Descriptions of the symbols used in this table are ...
Page 111
DC and Switching Characteristics Internal Logic V V GND level Table 9: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V for Drivers CCO IOSTANDARD Min Nom Attribute (V) (V) LVDS_25 2.375 2.50 BLVDS_25 2.375 2.50 MINI_LVDS_25 2.375 ...
Page 112
R Internal Logic V OUTN V OUTP GND level Table 10: DC Characteristics of User I/Os Using Differential Signal Standards V OD IOSTANDARD Min Typ Attribute (mV) (mV) LVDS_25 250 350 BLVDS_25 250 350 MINI_LVDS_25 300 - RSDS_25 100 - ...
Page 113
... For more complete, more precise, and worst-case 10 data, use the values reported by the Xilinx static timing ana- lyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 11: Spartan-3E v1.10 Speed Grade Designations Device Preview Advance XC3S100E –4 XC3S250E –4 XC3S500E –4 XC3S1200E –4 XC3S1600E – ...
Page 114
R Table 12: Recommended Operating Conditions for the DLL Symbol Input Frequency Ranges F CLKIN_FREQ_DLL CLKIN Notes: 1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. 2. Use ...
Page 115
DC and Switching Characteristics Table 14: Recommended Operating Conditions for the DFS Symbol (2) Input Frequency Ranges F CLKIN_FREQ_FX CLKIN Notes: 1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use both ...
Page 116
... CCINT CCAUX CCO Table www.xilinx.com DC and Switching Characteristics T ICCK DS312-3_01_020505 All Speed Grades Device Min Max XC3S100E - 5 XC3S250E - 5 XC3S500E - 5 XC3S1200E - 5 XC3S1600E - 7 All 0.3 - XC3S100E - 2 XC3S250E - 2 XC3S500E - 2 XC3S1200E - 2 XC3S1600E - 3 All 0.5 4.0 4. This means power must be applied to all V 1.2V 2.5V Units µ ...
Page 117
DC and Switching Characteristics PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 4: Waveforms for Master and Slave Serial Configuration Table 17: Timing for the Master and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time ...
Page 118
R PROG_B (Input) INIT_B (Open-Drain) CS_B (Input) RDWR_B (Input) CCLK (Input (Inputs) High-Z BUSY (Output) Notes possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or ...
Page 119
DC and Switching Characteristics Table 18: Timing for the Slave Parallel Configuration Mode (Continued) Symbol Hold Times T The time from the rising transition at the CCLK pin to the point when data is SMCCD last held at the D0-D7 ...
Page 120
R TCK (Input) TMS (Input) TDI (Input) TDO (Output) Table 19: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin TCKTDO to data appearing at the TDO pin ...
Page 121
DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. The Spartan-3E Family Data Sheet DS312-1, Spartan-3E FPGA Family: DS312-2, Spartan-3E FPGA Family: DS312-3, Spartan-3E FPGA Family: ...
Page 122
R DS312-4 (v1.1) March 21, 2005 Introduction This section describes the various pins on a Spartan™-3E FPGA and how they connect within the supported compo- nent packages. Table 1: Types of Pins on Spartan-3E FPGAs Type / Color Code I/O ...
Page 123
Pinout Descriptions Table 1: Types of Pins on Spartan-3E FPGAs Type / Color Code JTAG Dedicated JTAG pin. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX. GND Dedicated ground ...
Page 124
R Package Overview Table 2 shows the eight low-cost, space-saving production package styles for the Spartan-3E family. Each package style is available as a standard and an environmen- tally-friendly lead-free (Pb-free) option. The Pb-free pack- ages include an extra ‘G’ ...
Page 125
Pinout Descriptions Mechanical Drawings Detailed mechanical drawings for each package type are available from the Xilinx website at the specified location in Table 4. Table 4: Xilinx Package Mechanical Drawings Package VQ100 / VQG100 http://www.xilinx.com/bvdocs/packages/vq100.pdf CP132 / CPG132 http://www.xilinx.com/bvdocs/packages/cp132.pdf TQ144 ...
Page 126
... R Table 6: Maximum User I/O by Package Maximum Device Package User I/Os XC3S100E 66 VQ100 XC3S250E 66 XC3S250E 92 CP132 XC3S500E 92 XC3S100E 108 TQ144 XC3S250E 108 XC3S250E 158 PQ208 XC3S500E 158 XC3S250E 172 XC3S500E FT256 190 XC3S1200E 190 XC3S500E 232 XC3S1200E FG320 250 XC3S1600E 250 XC3S1200E ...
Page 127
... Pinout Descriptions VQ100: 100-lead Very-thin Quad Flat Package The XC3S100E and the XC3S250E devices are available in the 100-lead very-thin quad flat package, VQ100. Both devices share a common footprint for this package as shown in Table 7 and Figure 2. Table 7 lists all the package pins. They are sorted by bank number and then by pin name of the largest device ...
Page 128
... P14 GND P19 GND P29 GND P37 GND P52 GND P59 GND P64 GND P72 GND P81 GND www.xilinx.com Pinout Descriptions XC3S100E VQ100 XC3S250E Pin Pin Name Number GND P87 GND P93 P51 P1 P77 P100 P76 P75 P21 P46 P74 P96 ...
Page 129
... Pinout Descriptions User I/Os by Bank Table 8 indicates how the 66 available user-I/O pins are dis- tributed between the four I/O banks on the VQ100 package. Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package Package Maximum Edge I/O Bank I/O ...
Page 130
R VQ100 Footprint In Figure 2, note pin 1 indicator in top-left corner and logo orientation. The engineering sample footprint is slightly dif- ferent. PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 5 VCCINT 6 GND 7 VCCO_3 8 ...
Page 131
Pinout Descriptions CP132: 132-ball Chip-scale Package The XC3S250E and the XC3S500E FPGAs are available in the 132-lead chip-scale package, CP132. Both devices share a common footprint for this package as shown in Table 10 and Figure 3. Table 10 lists ...
Page 132
R Table 10: CP132 Package Pinout XC3S250E XC3S500E Bank Pin Name 2 IO/M1 2 IO/VREF_2 2 IO_L01N_2/INIT_B 2 IO_L01P_2/CSO_B 2 IO_L02N_2/MOSI/CSI_B 2 IO_L02P_2/DOUT/BUSY 2 IO_L03N_2/D6/GCLK13 2 IO_L03P_2/D7/GCLK12 2 IO_L04N_2/D3/GCLK15 2 IO_L04P_2/D4/GCLK14 2 IO_L06N_2/D1/GCLK3 2 IO_L06P_2/D2/GCLK2 2 IO_L07N_2/DIN/D0 2 IO_L07P_2/M0 2 ...
Page 133
Pinout Descriptions Table 10: CP132 Package Pinout XC3S250E XC3S500E Bank Pin Name GND GND GND GND VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX Table 11: User I/Os Per Bank ...
Page 134
R CP132 Footprint I/O A PROG_B TDI GND L11P_0 I/O I/O I/O I/O B L11N_0 L01N_3 L01P_3 L10P_0 HSWAP I/O I/O I/O C GND L02N_3 L02P_3 L10N_0 I/O I/O D VCCINT L03N_3 L03P_3 INPUT E VCCO_3 GND ...
Page 135
... Pinout Descriptions TQ144: 144-lead Thin Quad Flat Package The XC3S100E and the XC3S250E FPGAs are available in the 144-lead thin quad flat package, TQ144. Both devices share a common footprint for this package as shown in Table 12 and Figure 4. Table 12 lists all the package pins. They are sorted by bank number and then by pin name of the largest device ...
Page 136
... R Table 12: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 0 VCCO_0 0 VCCO_0 1 IO/A0 1 IO/VREF_1 1 IO_L01N_1/A15 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 1 IO_L03N_1/A11 1 IO_L03P_1/A12 1 IO_L04N_1/A9/RHCLK1 1 IO_L04P_1/A10/RHCLK0 1 IO_L05N_1/A7/RHCLK3/TRDY1 1 IO_L05P_1/A8/RHCLK2 1 IO_L06N_1/A5/RHCLK5 1 IO_L06P_1/A6/RHCLK4/IRDY1 1 IO_L07N_1/A3/RHCLK7 1 IO_L07P_1/A4/RHCLK6 1 IO_L08N_1/A1 1 IO_L08P_1/A2 1 IO_L09N_1/LDC0 1 IO_L09P_1/HDC 1 IO_L10N_1/LDC2 1 IO_L10P_1/LDC1 IP/VREF_1 1 VCCO_1 1 VCCO_1 2 IO/D5 2 IO/M1 2 IP/VREF_2 DS312-4 (v1.1) March 21, 2005 ...
Page 137
... Pinout Descriptions Table 12: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 2 IO_L01N_2/INIT_B 2 IO_L01P_2/CSO_B 2 IO_L02N_2/MOSI/CSI_B 2 IO_L02P_2/DOUT/BUSY 2 IO_L04N_2/D6/GCLK13 2 IO_L04P_2/D7/GCLK12 2 IO_L05N_2/D3/GCLK15 2 IO_L05P_2/D4/GCLK14 2 IO_L07N_2/D1/GCLK3 2 IO_L07P_2/D2/GCLK2 2 IO_L08N_2/DIN/D0 2 IO_L08P_2/M0 2 IO_L09N_2/VS1/A18 2 IO_L09P_2/VS2/A19 2 IO_L10N_2/CCLK 2 IO_L10P_2/VS0/A17 IP_L03N_2/VREF_2 2 IP_L03P_2 2 IP_L06N_2/M2/GCLK1 2 IP_L06P_2/RDWR_B/GCLK0 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IP/VREF_3 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 ...
Page 138
... R Table 12: TQ144 Package Pinout (Continued) Bank XC3S100E Pin Name 3 IO_L05N_3/LHCLK3/IRDY2 3 IO_L05P_3/LHCLK2 3 IO_L06N_3/LHCLK5 3 IO_L06P_3/LHCLK4/TRDY2 3 IO_L07N_3/LHCLK7 3 IO_L07P_3/LHCLK6 3 IO_L08N_3 3 IO_L08P_3 3 IO_L09N_3 3 IO_L09P_3 3 IO_L10N_3 3 IO_L10P_3 IP/VREF_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
Page 139
... User I/Os by Bank Table 13 and Table 14 indicate how the 108 available user-I/O pins are distributed between the four I/O banks on the TQ144 package. Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package Package Maximum Edge I/O Bank Top 0 Right ...
Page 140
... Advance Product Specification The arrows indicate the direction for easy migration. For example, a left-facing arrow indicates that the pin on the XC3S250E unconditionally migrates to the pin on the XC3S100E. It may be possible to migrate the opposite direction depending on the I/O configuration. For example, Table 15 uncondi- an I/O pin (Type = I/O) can migrate to an input-only pin (Type = INPUT) if the I/O pin is configured as an input ...
Page 141
... I/O INPUT: Unrestricted, 21 general-purpose input pin CONFIG: Dedicated 2 configuration pins N.C.: Not connected 0 20 between the XC3S100E and XC3S250E. Engineering sam- ple footprint is slightly different. Bank 0 Bank 2 DUAL: Configuration pin, then 42 possible user I/O GCLK: User I/O, input global buffer input ...
Page 142
R PQ208: 208-pin Plastic Quad Flat Package The 208-pin plastic quad flat package, PQ208, supports two different Spartan-3E FPGAs, including the XC3S250E and the XC3S500E. Table 17 lists all the PQ208 package pins. They are sorted by bank number and ...
Page 143
Pinout Descriptions Table 17: PQ208 Package Pinout XC3S250E XC3S500E Bank Pin Name 1 IO_L09N_1/A5/RHCLK5 1 IO_L09P_1/A6/RHCLK4 1 IO_L10N_1/A3/RHCLK7 1 IO_L10P_1/A4/RHCLK6 1 IO_L11N_1/A1 1 IO_L11P_1/A2 1 IO_L12N_1/A0 1 IO_L12P_1 1 IO_L13N_1 1 IO_L13P_1 1 IO_L14N_1 1 IO_L14P_1 1 IO_L15N_1/LDC0 1 IO_L15P_1/HDC ...
Page 144
R Table 17: PQ208 Package Pinout XC3S250E XC3S500E Bank Pin Name 2 VCCO_2 2 VCCO_2 3 IO/VREF_3 3 IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 IO_L04N_3 3 IO_L04P_3 3 IO_L05N_3 3 IO_L05P_3 3 IO_L06N_3 3 ...
Page 145
Pinout Descriptions Table 17: PQ208 Package Pinout XC3S250E XC3S500E Bank Pin Name VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT Table 18: User I/Os ...
Page 146
R PQ208 Footprint (Left) DS312-4 (v1.1) March 21, 2005 Advance Product Specification PROG_B 1 IO_L01P_3 2 IO_L01N_3 3 IO_L02P_3 4 IO_L02N_3/VREF_3 VCCAUX 7 IO_L03P_3 8 IO_L03N_3 9 GND 10 IO_L04P_3 11 IO_L04N_3 12 VCCINT ...
Page 147
Pinout Descriptions PQ208 Footprint (Right) Bank 0 Bank 2 26 156 GND 155 TMS 154 IP 153 IO_L16N_1/LDC2 152 IO_L16P_1/LDC1 151 IO_L15N_1/LDC0 150 IO_L15P_1/HDC 149 VCCAUX 148 IP 147 IO_L14N_1 146 IO_L14P_1 145 IO_L13N_1 144 IO_L13P_1 143 VCCO_1 142 IP ...
Page 148
R FT256: 256-ball Fine-pitch, Thin Ball Grid Array The 256-lead fine-pitch, thin ball grid array package, FT256, supports three different Spartan-3E FPGAs, including the XC3S250E, the XC3S500E, and the XC3S1200E. Table 19 lists all the package pins. They are sorted ...
Page 149
Pinout Descriptions Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 0 IO_L09P_0/GCLK6 0 IO_L11N_0/GCLK11 0 IO_L11P_0/GCLK10 0 IO_L12N_0 0 IO_L12P_0 IO_L14N_0/VREF_0 0 IO_L14P_0 0 IO_L15N_0 0 IO_L15P_0 0 IO_L17N_0/VREF_0 ...
Page 150
R Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 1 IO_L01P_1/A16 1 IO_L02N_1/A13 1 IO_L02P_1/A14 IO_L04N_1/VREF_1 1 IO_L04P_1 IO_L06N_1 1 ...
Page 151
Pinout Descriptions Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 1 IO_L15P_1 1 IO_L16N_1 1 IO_L16P_1 IO_L18N_1/LDC0 1 IO_L18P_1/HDC 1 IO_L19N_1/LDC2 1 IO_L19P_1/LDC1 ...
Page 152
R Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 2 IO/D5 2 IO/M1 2 IO/VREF_2 2 IO/VREF_2 2 IO_L01N_2/INIT_B 2 IO_L01P_2/CSO_B 2 IO_L03N_2/MOSI/CSI_B 2 IO_L03P_2/DOUT/BUSY 2 IO_L04N_2 2 IO_L04P_2 2 IO_L05N_2 2 IO_L05P_2 2 IO_L06N_2 2 IO_L06P_2 2 ...
Page 153
Pinout Descriptions Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 2 IO_L16P_2/A23 2 IO_L18N_2/A20 2 IO_L18P_2/A21 2 IO_L19N_2/VS1/A18 2 IO_L19P_2/VS2/A19 2 IO_L20N_2/CCLK 2 IO_L20P_2/VS0/A17 IP_L02N_2 2 IP_L02P_2 2 IP_L08N_2/VREF_2 2 IP_L08P_2 2 IP_L11N_2/M2/GCLK1 ...
Page 154
R Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name 3 IO_L06N_3 3 IO_L06P_3 3 IO_L07N_3 3 IO_L07P_3 3 IO_L08N_3/LHCLK1 3 IO_L08P_3/LHCLK0 3 IO_L09N_3/LHCLK3/ IRDY2 3 IO_L09P_3/LHCLK2 3 IO_L10N_3/LHCLK5 3 IO_L10P_3/LHCLK4/ TRDY2 3 IO_L11N_3/LHCLK7 3 IO_L11P_3/LHCLK6 3 IO_L12N_3 3 ...
Page 155
Pinout Descriptions Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name IP/VREF_3 3 IO/VREF_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 ...
Page 156
R Table 19: FT256 Package Pinout (Continued) Bank XC3S250E Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX ...
Page 157
Pinout Descriptions User I/Os by Bank Table 20, Table 21, and Table 22 indicate how the available user-I/O pins are distributed between the four I/O banks on the FT256 package. Table 20: User I/Os Per Bank on XC3S250E in the ...
Page 158
R Footprint Migration Differences Table 23 summarizes any footprint and functionality differ- ences between the XC3S250E, the XC3S500E, and the XC3S1200E FPGAs that may affect easy migration between devices in the FG256 package. There are 26 such balls. All other ...
Page 159
Pinout Descriptions FT256 Footprint I/O A GND TDI INPUT L17N_0 VREF_0 I/O I/O I/O B I/O L19N_0 L01P_3 L01N_3 HSWAP I/O I/O I/O I/O C L02N_3 L02P_3 L19P_0 L18N_0 VREF_3 I/O D INPUT VCCINT PROG_B L05P_3 ...
Page 160
R FG320: 320-ball Fine-pitch Ball Grid Array The 320-lead fine-pitch ball grid array package, FG320, supports three different Spartan-3E FPGAs, including the XC3S500E, the XC3S1200E, and the XC3S1600E, as shown in Table 24 and Figure 8. The FG320 package is ...
Page 161
Pinout Descriptions Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 0 IO_L08N_0 0 IO_L08P_0 0 IO_L09N_0 0 IO_L09P_0 0 IO_L11N_0/GCLK5 0 IO_L11P_0/GCLK4 0 IO_L12N_0/GCLK7 0 IO_L12P_0/GCLK6 0 IO_L14N_0/GCLK11 0 IO_L14P_0/GCLK10 0 IO_L15N_0 0 IO_L15P_0 0 IO_L17N_0 0 IO_L17P_0 ...
Page 162
R Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name IP_L02N_0 0 IP_L02P_0 0 IP_L07N_0 0 IP_L07P_0 0 IP_L10N_0 0 IP_L10P_0 0 IP_L13N_0/GCLK9 0 IP_L13P_0/GCLK8 0 IP_L16N_0 0 IP_L16P_0 0 IP_L22N_0 0 IP_L22P_0 0 VCCO_0 0 ...
Page 163
Pinout Descriptions Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 1 IO_L06P_1 1 IO_L07N_1 1 IO_L07P_1 1 IO_L08N_1 1 IO_L08P_1 1 IO_L09N_1/A11 1 IO_L09P_1/A12 1 IO_L10N_1/VREF_1 1 IO_L10P_1 1 IO_L11N_1/A9/RHCLK1 1 IO_L11P_1/A10/RHCLK0 1 IO_L12N_1/A7/RHCLK3/ TRDY1 1 IO_L12P_1/A8/RHCLK2 1 ...
Page 164
R Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 1 N. IO_L23N_1/LDC0 1 IO_L23P_1/HDC 1 IO_L24N_1/LDC2 1 IO_L24P_1/LDC1 ...
Page 165
Pinout Descriptions Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name N. IO/D5 2 IO/M1 2 IO/VREF_2 2 IO/VREF_2 2 IO_L01N_2/INIT_B 2 IO_L01P_2/CSO_B 2 IO_L03N_2/MOSI/CSI_B 2 IO_L03P_2/DOUT/BUSY 2 IO_L04N_2 2 IO_L04P_2 2 IO_L05N_2 ...
Page 166
R Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 2 IO_L16P_2/M0 2 IO_L18N_2 2 IO_L18P_2 2 IO_L19N_2/VREF_2 2 IO_L19P_2 2 IO_L20N_2 2 IO_L20P_2 IO_L22N_2/A22 2 IO_L22P_2/A23 2 IO_L24N_2/A20 2 ...
Page 167
Pinout Descriptions Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 N. IO_L01N_3 3 IO_L01P_3 3 IO_L02N_3/VREF_3 3 IO_L02P_3 3 IO_L03N_3 3 IO_L03P_3 3 N.C. ...
Page 168
R Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name 3 IO_L13N_3/LHCLK5 3 IO_L13P_3/LHCLK4/ TRDY2 3 IO_L14N_3/LHCLK7 3 IO_L14P_3/LHCLK6 3 IO_L15N_3 3 IO_L15P_3 3 IO_L16N_3 3 IO_L16P_3 3 IO_L17N_3/VREF_3 3 IO_L17P_3 3 IO_L18N_3 3 IO_L18P_3 3 IO_L19N_3 3 IO_L19P_3 ...
Page 169
Pinout Descriptions Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name IP/VREF_3 3 IO/VREF_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND ...
Page 170
R Table 24: FG320 Package Pinout (Continued) Bank XC3S500E Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX DONE VCCAUX PROG_B VCCAUX TCK VCCAUX TDI VCCAUX TDO VCCAUX ...
Page 171
Pinout Descriptions User I/Os by Bank Table 25, Table 26, and Table 27 indicate how the available user-I/O pins are distributed between the four I/O banks on the FG320 package. Table 25: User I/Os Per Bank for XC3S500E in the ...
Page 172
R can migrate to an input-only pin (Type = INPUT) if the I/O pin is configured as an input. Table 28: FG320 Footprint Migration Differences Pin Bank XC3S500E Migration A7 0 INPUT A12 ...
Page 173
Pinout Descriptions FG320 Footprint I/O INPUT A GND TDI INPUT L24P_0 L22P_0 I/O I/O INPUT B PROG_B GND L25N_0 L24N_0 L22N_0 HSWAP I/O I/O I/O C I/O L01P_3 L01N_3 L25P_0 L23P_0 I/O I/O I/O D INPUT ...
Page 174
R FG400: 400-ball Fine-pitch Ball Grid Array The 400-ball fine-pitch ball grid array, FG400, supports two different Spartan-3E FPGAs, including the XC3S1200E and the XC3S1600E. Both devices share a common footprint for this package as shown in Table 29 Table ...
Page 175
Pinout Descriptions Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name IP_L02N_0 0 IP_L02P_0 0 IP_L05N_0 0 IP_L05P_0 0 IP_L08N_0 0 IP_L08P_0 0 IP_L10N_0 0 IP_L10P_0 0 IP_L13N_0 0 IP_L13P_0 0 IP_L16N_0/GCLK9 0 IP_L16P_0/GCLK8 ...
Page 176
R Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name 1 IO_L19N_1/A0 1 IO_L19P_1 1 IO_L20N_1 1 IO_L20P_1 1 IO_L21N_1 1 IO_L21P_1 1 IO_L22N_1 1 IO_L22P_1 1 IO_L23N_1 1 IO_L23P_1 1 IO_L24N_1/VREF_1 1 IO_L24P_1 1 IO_L25N_1 1 IO_L25P_1 1 ...
Page 177
Pinout Descriptions Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name 2 IO_L10N_2 2 IO_L10P_2 2 IO_L12N_2 2 IO_L12P_2 2 IO_L13N_2 2 IO_L13P_2 2 IO_L15N_2/D6/GCLK13 2 IO_L15P_2/D7/GCLK12 2 IO_L16N_2/D3/GCLK15 2 IO_L16P_2/D4/GCLK14 2 IO_L18N_2/D1/GCLK3 2 IO_L18P_2/D2/GCLK2 2 IO_L19N_2/DIN/D0 2 IO_L19P_2/M0 ...
Page 178
R Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name 3 IO_L03N_3 3 IO_L03P_3 3 IO_L04N_3 3 IO_L04P_3 3 IO_L05N_3 3 IO_L05P_3 3 IO_L06N_3 3 IO_L06P_3 3 IO_L07N_3 3 IO_L07P_3 3 IO_L08N_3 3 IO_L08P_3 3 IO_L09N_3/VREF_3 3 IO_L09P_3 3 ...
Page 179
Pinout Descriptions Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name 3 IP/VREF_3 3 IP/VREF_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND ...
Page 180
R Table 29: FG400 Package Pinout XC3S1200E XC3S1600E Bank Pin Name VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Table 30: User I/Os Per Bank for the XC3S250E and XC3S500E in the ...
Page 181
Pinout Descriptions FG400 Footprint Left Half of Package (top view) I/O: Unrestricted, 156 general-purpose user I/O INPUT: User I reference resistor input for bank DUAL: Configuration pin, 46 then possible user I/O VREF: User I/O or input 24 ...
Page 182
R Bank I/O I/O I/O GND I/O L09N_0 L09P_0 L06N_0 VREF_0 INPUT INPUT I/O I/O GND L13N_0 L13P_0 L10N_0 L06P_0 I/O I/O I/O I/O INPUT VREF_0 L11N_0 L10P_0 L07N_0 L05P_0 I/O I/O INPUT VCCAUX ...
Page 183
Pinout Descriptions FG484: 484-ball Fine-pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FG484, supports the XC3S1600E FPGA. Table 31 lists all the FG484 package pins. They are sorted by bank number and then by pin name. Pairs of ...
Page 184
R Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 0 IO_L33P_0 0 IO_L35N_0 0 IO_L35P_0 0 IO_L36N_0 0 IO_L36P_0 0 IO_L38N_0/VREF_0 0 IO_L38P_0 0 IO_L39N_0 0 IO_L39P_0 0 IO_L40N_0/HSWAP 0 IO_L40P_0 IP_L02N_0 0 IP_L02P_0 ...
Page 185
Pinout Descriptions Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 1 IO_L15N_1 1 IO_L15P_1 1 IO_L16N_1/A11 1 IO_L16P_1/A12 1 IO_L17N_1/VREF_1 1 IO_L17P_1 1 IO_L18N_1/A9/RHCLK1 1 IO_L18P_1/A10/RHCLK0 1 IO_L19N_1/A7/RHCLK3/ TRDY1 1 IO_L19P_1/A8/RHCLK2 1 IO_L20N_1/A5/RHCLK5 1 IO_L20P_1/A6/RHCLK4/ IRDY1 1 IO_L21N_1/A3/RHCLK7 1 ...
Page 186
R Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 1 IP/VREF_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 ...
Page 187
Pinout Descriptions Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 2 IO_L32N_2 2 IO_L32P_2 2 IO_L33N_2 2 IO_L33P_2 2 IO_L35N_2/A22 2 IO_L35P_2/A23 2 IO_L36N_2 2 IO_L36P_2 2 IO_L38N_2/A20 2 IO_L38P_2/A21 2 IO_L39N_2/VS1/A18 2 IO_L39P_2/VS2/A19 2 IO_L40N_2/CCLK 2 IO_L40P_2/VS0/A17 2 ...
Page 188
R Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 3 IO_L14N_3 3 IO_L14P_3 3 IO_L15N_3 3 IO_L15P_3 3 IO_L16N_3 3 IO_L16P_3 3 IO_L17N_3 3 IO_L17P_3 3 IO_L18N_3/LHCLK1 3 IO_L18P_3/LHCLK0 3 IO_L19N_3/LHCLK3/IRDY2 3 IO_L19P_3/LHCLK2 3 IO_L20N_3/LHCLK5 3 IO_L20P_3/LHCLK4/TRDY2 3 IO_L21N_3/LHCLK7 ...
Page 189
Pinout Descriptions Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
Page 190
R Table 31: FG484 Package Pinout XC3S1600E Bank Pin Name VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT Table 32: User I/Os Per Bank for the XC3S1600E in ...
Page 191
Pinout Descriptions FG484 Footprint Left Half of Package (top view) I/O: Unrestricted, 214 general-purpose user I/O INPUT: User I reference resistor input for bank DUAL: Configuration pin, 46 then possible user I/O VREF: User I/O or input 28 ...
Page 192
R Bank I/O INPUT INPUT I/O I/O I/O L12N_0 L17N_0 L17P_0 L12P_0 L07N_0 L07P_0 VREF_0 I/O I/O INPUT I/O GND VCCO_0 L19P_0 L09N_0 L05P_0 GCLK6 VREF_0 I/O INPUT I/O I/O INPUT I/O L19N_0 L14P_0 ...
Page 193
Pinout Descriptions Revision History The following table shows the revision history for this document. Date Version 03/01/05 1.0 Initial Xilinx release. 03/21/05 1.1 Added XC3S250E in the CP132 package to pairs on CP132. Added pinout and footprint information for the ...