XC6SLX25-3FGG484I

Manufacturer Part NumberXC6SLX25-3FGG484I
DescriptionIC FPGA SPARTAN 6 24K 484FGGBGA
ManufacturerXilinx Inc
SeriesSpartan® 6 LX
XC6SLX25-3FGG484I datasheets

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Specifications of XC6SLX25-3FGG484I

Number Of Logic Elements/cells24051Number Of Labs/clbs1879
Total Ram Bits958464Number Of I /o266
Voltage - Supply1.14 V ~ 1.26 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case484-BBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
XC6SLX45-2FGG484CES PDF datasheetXC6SLX45-2FGG484CES PDF datasheet #2
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DS160 (v1.7) March 21, 2011
General Description
The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The
thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous
Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that
delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-
up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation
DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power-
optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management
modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-
cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for
high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable
designers to focus on innovation as soon as their development cycle begins.
Summary of Spartan-6 FPGA Features
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Spartan-6 Family:
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Spartan-6 LX FPGA: Logic optimized
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Spartan-6 LXT FPGA: High-speed serial connectivity
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Designed for low cost
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Multiple efficient integrated blocks
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Optimized selection of I/O standards
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Staggered pads
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High-volume plastic wire-bonded packages
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Low static and dynamic power
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45 nm process optimized for cost and low power
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Hibernate power-down mode for zero power
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Suspend mode maintains state and configuration with
multi-pin wake-up, control enhancement
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Lower-power 1.0V core voltage (LX FPGAs, -1L only)
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High performance 1.2V core voltage (LX and LXT
FPGAs, -2, -3, and -3N speed grades)
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Multi-voltage, multi-standard SelectIO™ interface banks
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Up to 1,080 Mb/s data transfer rate per differential I/O
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Selectable output drive, up to 24 mA per pin
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3.3V to 1.2V I/O standards and protocols
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Low-cost HSTL and SSTL memory interfaces
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Hot swap compliance
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Adjustable I/O slew rates to improve signal integrity
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High-speed GTP serial transceivers in the LXT FPGAs
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Up to 3.2 Gb/s
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High-speed interfaces including: Serial ATA, Aurora,
1G Ethernet, PCI Express, OBSAI, CPRI, EPON,
GPON, DisplayPort, and XAUI
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Integrated Endpoint block for PCI Express designs (LXT)
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Low-cost PCI® technology support compatible with the
33 MHz, 32- and 64-bit specification.
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Efficient DSP48A1 slices
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High-performance arithmetic and signal processing
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Fast 18 x 18 multiplier and 48-bit accumulator
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Pipelining and cascading capability
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Pre-adder to assist filter applications
© 2009–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States
and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS160 (v1.7) March 21, 2011
Preliminary Product Specification
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Integrated Memory Controller blocks
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Abundant logic resources with increased logic capacity
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Block RAM with a wide range of granularity
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Clock Management Tile (CMT) for enhanced performance
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Simplified configuration, supports low-cost standards
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Enhanced security for design protection
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Faster embedded processing with enhanced, low cost,
MicroBlaze™ soft processor
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Industry-leading IP and reference designs
www.xilinx.com
Spartan-6 Family Overview
Preliminary Product Specification
DDR, DDR2, DDR3, and LPDDR support
Data rates up to 800 Mb/s ( 12.8 Gb/s peak bandwidth)
Multi-port bus structure with independent FIFO to reduce
design timing issues
Optional shift register or distributed RAM support
Efficient 6-input LUTs improve performance and
minimize power
LUT with dual flip-flops for pipeline centric applications
Fast block RAM with byte write enable
18 Kb blocks that can be optionally programmed as two
independent 9 Kb block RAMs
Low noise, flexible clocking
Digital Clock Managers (DCMs) eliminate clock skew
and duty cycle distortion
Phase-Locked Loops (PLLs) for low-jitter clocking
Frequency synthesis with simultaneous multiplication,
division, and phase shifting
Sixteen low-skew global clock networks
2-pin auto-detect configuration
Broad third-party SPI (up to x4) and NOR flash support
Feature rich Xilinx Platform Flash with JTAG
MultiBoot support for remote upgrade with multiple
bitstreams, using watchdog protection
Unique Device DNA identifier for design authentication
AES bitstream encryption in the larger devices
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XC6SLX25-3FGG484I Summary of contents

  • Page 1

    DS160 (v1.7) March 21, 2011 General Description The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power ...

  • Page 2

    ... XC6SLX25 24,051 3,758 30,064 XC6SLX45 43,661 6,822 54,576 XC6SLX75 74,637 11,662 93,296 XC6SLX100 101,261 15,822 126,576 XC6SLX150 147,443 23,038 184,304 XC6SLX25T 24,051 3,758 30,064 XC6SLX45T 43,661 6,822 54,576 XC6SLX75T 74,637 11,662 93,296 XC6SLX100T 101,261 15,822 126,576 XC6SLX150T 147,443 23,038 184,304 Notes: 1 ...

  • Page 3

    ... XC6SLX9 106 102 XC6SLX16 106 XC6SLX25 XC6SLX45 XC6SLX75 XC6SLX100 XC6SLX150 XC6SLX25T XC6SLX45T XC6SLX75T XC6SLX100T XC6SLX150T Notes: 1. There is no memory controller on the devices in these packages. 2. Memory controller block support the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the XC6SLX4 ...

  • Page 4

    ... FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial flash PROM. The Spartan-6 FPGA can configure itself via BPI when connected to an industry-standard parallel NOR flash. Note that BPI configuration is not supported in the XC6SLX4, XC6SLX25, and XC6SLX25T nor is BPI available when using Spartan-6 FPGAs in TQG144 and CPG196 packages. ...

  • Page 5

    Clock Management Each Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually or concatenated. DCM The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, ...

  • Page 6

    Block RAM Every Spartan-6 FPGA has between 12 and 268 dual-port block RAMs, each storing 18 Kb. Each block RAM has two completely independent ports that share only the stored data. Synchronous Operation Each memory access, whether read or write, ...

  • Page 7

    Input/Output The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 3.3V. The Spartan-6 FPGA SelectIO Resources ...

  • Page 8

    Low-Power Gigabit Transceiver Ultra-fast data transmission between ICs, over the backplane, or over longer distances is becoming increasingly popular and important. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity issues at these ...

  • Page 9

    Spartan-6 FPGA Ordering Information The Spartan-6 FPGA ordering information shown in X-Ref Target - Figure 1 Example: XC6SLX100T-2FGG676C Device Type Speed Grade (1) (-L1 , -2, -3, -N3 Note: 1) -L1 is the ordering code for the lower power, -1L ...

  • Page 10

    ... Input and Output www.xilinx.com Spartan-6 Family Overview Multi-voltage, multi-standard SelectIO™ interface sections on page 1. Clarified PCI support on 2, revised user I/O counts, removed the XC6SLX25 in CLBs, Slices, and LUTs, Frequency Block. Clarified I/O pin range, V section. and Table 2 including adding the XC6SLX75 and section ...

  • Page 11

    Spartan-6 FPGA Documentation Complete and up-to-date documentation of the Spartan-6 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/support/documentation/spartan-6.htm. In addition to the most recent Spartan-6 Family Overview, the following files are also available for download: Spartan-6 FPGA ...

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