XCV200E-6PQ240I Xilinx Inc, XCV200E-6PQ240I Datasheet
XCV200E-6PQ240I
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XCV200E-6PQ240I Summary of contents
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R DS022-1 (v2.3) July 17, 2002 Features • Fast, High-Density 1.8 V FPGA Family - Densities from system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant ...
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... Virtex™-E 1.8 V Field Programmable Gate Arrays Table 1: Virtex-E Field-Programmable Gate Array Family Members System Device Gates Gates XCV50E 71,693 20,736 XCV100E 128,236 32,400 XCV200E 306,393 63,504 XCV300E 411,955 82,944 XCV400E 569,952 129,600 XCV600E 985,882 186,624 XCV1000E 1,569,178 331,776 XCV1600E 2,188,742 ...
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R resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Virtex-E Ordering Information Example: XCV300E-6PQ240C Device Type Speed Grade (-6, -7, -8) Revision History The following table shows the revision history for this document. Date Version 12/7/99 1.0 Initial Xilinx release. 1/10/00 1.1 ...
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R Date Version • Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to 11/20/00 1.8 Preliminary. • Updated minimums in Table 13 and added notes to Table 14. • Added to note 2 to Absolute Maximum Ratings. • ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-1 (v2.3) July 17, 2002 Production Product Specification ...
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R DS022-2 (v2.8) January 16, 2006 Architectural Description Virtex-E Array The Virtex-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Table 1: Supported I/O Standards I/O Output Input Standard V V CCO CCO LVTTL 3.3 3.3 LVCMOS2 2.5 2.5 LVCMOS18 1.8 1.8 SSTL3 I & II 3.3 N/A SSTL2 I & II 2.5 ...
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R Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure multiple V pins, all of which must be connected to the CCO same voltage. This voltage is determined by the output ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays G4 G3 LUT LUT F5IN CLK CE Storage Elements The storage elements in the ...
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... Table 4 is available in each Virtex-E device. Table 4: Virtex-E Block SelectRAM Amounts Virtex-E Device # of Blocks Block SelectRAM Bits XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E Dedicated Routing. XCV1600E XCV2000E XCV2600E XCV3200E As illustrated in fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 6: Dual-Port Block SelectRAM Table 5 shows the depth and width aspect ratios for the block SelectRAM. ...
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R Dedicated Routing Some classes of signal require dedicated routing resources to maximize performance. In the Virtex-E architecture, dedi- cated routing resources are provided for two classes of signal. • Horizontal routing resources are provided for on-chip 3-state buses. Four ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays The DLL also operates as a clock mirror. By driving the out- put from a DLL off-chip and then back on again, the DLL can be used to deskew a board level clock ...
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R IOB IOB IOB IOB IOB IOB IOB IOB IOB BYPASS REGISTER INSTRUCTION REGISTER TDI Instruction Set The Virtex-E series Boundary Scan instruction set also includes instructions to configure the device and read back configuration data (CFG_IN, CFG_OUT, and JSTART). ...
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... The USERCODE register is supported. By using the USER- CODE, a user-programmable identification code can be loaded and shifted out for examination. The identification code (see Table stream generation and is valid only after configuration. Table 7: IDCODEs Assigned to Virtex-E FPGAs FPGA XCV50E XCV100E XCV200E Figure 12. XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E ...
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R Development System Virtex-E FPGAs are supported by the Xilinx Foundation and Alliance Series CAE tools. The basic methodology for Virtex-E design consists of three interrelated steps: design entry, implementation, and verification. Industry-standard tools are used for design entry and ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays For in-circuit debugging, an optional download and read- back cable is available. This cable connects the FPGA in the target system workstation. After downloading the design into the FPGA, ...
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... R Table 9 lists the total number of bits required to configure each device. Table 9: Virtex-E Bitstream Lengths Device # of Configuration Bits XCV50E XCV100E XCV200E 1,442,016 XCV300E 1, 875,648 XCV400E 2,693,440 XCV600E 3,961,632 XCV1000E 6,587,520 XCV1600E 8,308,992 XCV2000E 10,159,648 XCV2600E 12,922,336 XCV3200E 16,283,712 Slave-Serial Mode In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or other source of serial configuration data ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays . Optional Pull-up 1 Resistor on Done PROGRAM Note 1: If none of the Virtex FPGAs have been selected to drive DONE, an external pull-up resistor of 330 Ω should be added to ...
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R Apply Power FPGA starts to clear configuration memory. Set PROGRAM = High FPGA makes a final clearing pass and releases Release INIT INIT when finished. INIT? Load a Configuration Bit Once per bitstream, FPGA checks data using CRC and ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays 3. At the rising edge of CCLK: If BUSY is Low, the data is accepted on this clock. If BUSY is High (from a previous write), the data is not accepted. Acceptance instead ...
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R Apply Power FPGA starts to clear configuration memory. PROGRAM from Low to High FPGA makes a final clearing pass and releases INIT when finished. Release INIT INIT? Set WRITE = Low Enter Data Source Set CS = Low Apply ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Configuration through the TAP uses the CFG_IN instruc- tion. This instruction allows data input on TDI to be con- verted into data packets for the internal configuration bus. The following steps are required ...
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R the internal storage elements to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed. In addi- tion, the GTS, GSR, and GWE events can be made depen- ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays CLKDLL CLKIN CLK0 CLK90 CLKFB CLK180 CLK270 CLK2X CLKDV RST LOCKED Figure 22: Standard DLL Symbol CLKDLL CLKDLLHF CLKIN CLK0 CLKFB CLK180 CLKDV RST LOCKED ds022_027_121099 Figure 23: High Frequency DLL Symbol CLKDLLHF ...
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R ground. As the DLL delay taps reset to zero, glitches can occur on the DLL clock output pins. Activation of the RST pin can also severely affect the duty cycle of the clock out- put pins. Furthermore, the DLL ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Properties Properties provide access to some of the Virtex-E series DLL features, (for example, clock division and duty cycle correction). Duty Cycle Correction Property The 1x clock outputs, CLK0, CLK90, CLK180, and ...
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R Useful Application Examples The Virtex-E DLL can be used in a variety of creative and useful applications. The following examples show some of the more common applications. The Verilog and VHDL example files are available at: ftp://ftp.xilinx.com/pub/applications/xapp/xapp132.zip Standard Usage ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Because any single DLL can access only two BUFGs at most, any additional output clock signals must be routed from the DLL in this example on the high speed backbone routing. The dll_2x ...
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R RAMB4_S#_S# WEA ENA DOA[#:0] RSTA CLKA ADDRA[#:0] DIA[#:0] WEB ENB RSTB DOB[#:0] CLKB ADDRB[#:0] DIB[#:0] Figure 31: Dual-Port Block SelectRAM+ Memory RAMB4_S RST DO[#:0] CLK ADDR[#:0] DI[#:0] ds022_033_121399 Figure 32: Single-Port Block SelectRAM+ Memory Table 14: Available ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Data Output Bus—DO[A|B]<#:0> The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. During a write operation, the data out bus ...
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R indicating that the block SelectRAM+ memory is now dis- abled. The DO bus retains the last value. Dual Port Timing Figure 34 shows a timing diagram for a true dual-port read/write block SelectRAM+ memory. The clock on port A ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays CLK_A ADDR_A EN_A WE_A DI_A DO_A CLK_B ADDR_B 00 EN_B WE_B DI_B 1111 DO_B MEM (00) Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory At the third rising edge ...
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R Initialization in Verilog and Synopsys The block SelectRAM+ structures can be initialized in Verilog for both simulation and synthesis for inclusion in the EDIF output file. The simulation of the Verilog code uses a def- param to pass the ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays VHDL Initialization Example library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE ...
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R Verilog Initialization Example module MYMEM (CLK, WE, ADDR, DIN, DOUT); input CLK, WE; input [8:0] ADDR; input [7:0] DIN; output [7:0] DOUT; wire logic0, logic1; //synopsys dc_script_begin //set_attribute ram0 INIT_00 "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string //set_attribute ram0 INIT_01 "FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Fundamentals Modern bus applications, pioneered by the largest and most influential companies in the digital electronics industry, are commonly introduced with a new I/O standard tailored spe- cifically to the needs of that ...
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R standard requires a Differential Amplifier input buffer and a Push-Pull output buffer. SSTL3 — Stub Series Terminated Logic for 3.3V The Stub Series Terminated Logic for 3.3V, or SSTL3 stan- dard is a general purpose 3.3V memory bus standard ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays The voltage reference signal is “banked” within the Virtex-E device on a half-edge basis such that for all packages there are eight independent V banks internally. See REF for a representation of the ...
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R represents a combination of the LVTTL IBUFG and BUFG symbols, such that the output of the BUFGP can connect directly to the clock pins throughout the design. Unlike previous architectures, the Virtex-E BUFGP symbol can only be placed in ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays LVTTL 3-state output buffers have selectable drive strengths. The format for LVTTL OBUFT symbol names is as follows: OBUFT_<slew_rate>_<drive_strength> where <slew_rate> is either F (Fast (Slow), and <drive_strength> is specified in ...
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R IOBUF x133_06_111699 Figure 42: Input/Output Buffer Symbol (IOBUF) The following list details variations of the IOBUF symbol. • IOBUF • IOBUF_S_2 • IOBUF_S_4 • IOBUF_S_6 • IOBUF_S_8 • IOBUF_S_12 • IOBUF_S_16 • IOBUF_S_24 • IOBUF_F_2 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Flip-Flop/Latch Property The Virtex-E series I/O Block (IOB) includes an optional register on the input path, an optional register on the output path, and an optional register on the 3-state control pin. ...
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R Input termination techniques include the following. • None • Parallel (Shunt) These termination techniques can be applied in any combi- nation. A generic example of each combination of termina- tion methods appears in Figure 43. Unterminated Double Parallel Terminated ...
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... HSTL Class III HSTL Class IV SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II CTT AGP Note: This analysis assumes load for each output. Table 22: Virtex-E Equivalent Power/Ground Pairs Pkg/Part XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E CS144 12 PQ240 20 HQ240 BG352 20 BG432 BG560 (1) ...
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R Application Examples Creating a design with the SelectI/O features requires the instantiation of the desired library symbol within the design code. At the board level, designers need to know the termi- nation techniques required for each I/O standard. This ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays HSTL A sample circuit illustrating a valid termination technique for HSTL_I appears in Figure 46. A sample circuit illustrating a valid termination technique for HSTL_III appears in Figure 47. Table 25: HSTL Class ...
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R SSTL3_I A sample circuit illustrating a valid termination technique for SSTL3_I appears in Figure 49. DC voltage specifications appear in Table 28. SSTL3 Class 3.3V CCO 50Ω 25Ω 1.5V ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays SSTL2_II A sample circuit illustrating a valid termination technique for SSTL2_II appears in Figure 52. DC voltage specifications appear in Table 31. SSTL2 Class 1.25V 2.5V CCO ...
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R LVTTL LVTTL requires no termination. DC voltage specifications appears in Table 34. Table 34: LVTTL Voltage Specifications Parameter Min V 3.0 CCO V - REF 2.0 IH −0 2 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays LVDS Depending on whether the device is transmitting an LVDS signal or receiving an LVDS signal, there are two different circuits used for LVDS termination. A sample circuit illustrat- ing a valid termination ...
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R Termination Resistor Packs Resistor packs are available with the values and the config- uration required for LVDS and LVPECL termination from Bourns, Inc., as listed in Table. For pricing and availability, please contact Bourns directly at http://www.bourns.com Table 40: ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Optional N-side Some designers might prefer to also instantiate the N-side buffer for the global clock buffer. This allows the top-level net list to include net connections for both PCB layout and sys- ...
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R Table 42: Input Library Macros Name Inputs IBUFDS_FD_LVDS I, IB, C IBUFDS_FDE_LVDS I, IB, CE, C IBUFDS_FDC_LVDS I, IB, C, CLR IBUFDS_FDCE_LVDS I, IB, CE, C, CLR IBUFDS_FDP_LVDS I, IB, C, PRE IBUFDS_FDPE_LVDS I, IB, CE, C, PRE IBUFDS_FDR_LVDS ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Table 43: Output Library Macros Name Inputs OBUFDS_FD_LVDS D, C OBUFDS_FDE_LVDS DD, CE, C OBUFDS_FDC_LVDS D, C, CLR OBUFDS_FDCE_LVDS D, CE, C, CLR OBUFDS_FDP_LVDS D, C, PRE OBUFDS_FDPE_LVDS D, CE, C, PRE OBUFDS_FDR_LVDS ...
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R The register elements can be packed in the IOB using the IOB property to TRUE on the register or by using the “map -pr [i|o|b]” where “i” is inputs only, “o” is outputs only and “b” is both inputs ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Table 44: Bidirectional I/O Library Macros Name IOBUFDS_FD_LVDS IOBUFDS_FDE_LVDS IOBUFDS_FDC_LVDS IOBUFDS_FDCE_LVDS IOBUFDS_FDP_LVDS IOBUFDS_FDPE_LVDS IOBUFDS_FDR_LVDS IOBUFDS_FDRE_LVDS IOBUFDS_FDS_LVDS IOBUFDS_FDSE_LVDS IOBUFDS_LD_LVDS IOBUFDS_LDE_LVDS IOBUFDS_LDC_LVDS IOBUFDS_LDCE_LVDS IOBUFDS_LDP_LVDS IOBUFDS_LDPE_LVDS Revision History The following table shows the revision history for ...
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R Date Version 9/20/00 1.7 • • • • • • • 11/20/00 1.8 • • • • • • • 2/12/01 1.9 • • • • • 4/02/01 2.0 • • 4/19/01 2.1 • 07/23/01 2.2 • • 11/09/01 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Virtex-E Data Sheet The Virtex-E Data Sheet contains the following modules: • DS022-1, Virtex-E 1.8V FPGAs: Introduction and Ordering Information (Module 1) • DS022-2, Virtex-E 1.8V FPGAs: Functional Description (Module 2) Module 2 ...
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... Table 1 correlates the current status of each Virtex-E device with a corresponding speed file designation. Table 1: Virtex-E Device Speed Grade Designations Speed Grade Designations Device Advance XCV50E XCV100E XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E All specifications are subject to change without notice. ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays DC Characteristics Absolute Maximum Ratings Symbol V Internal Supply voltage relative to GND CCINT V Supply voltage relative to GND CCO V Input Reference Voltage REF (3) V Input voltage relative to GND ...
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... XCV300E 300 mA XCV400E 300 mA XCV600E 400 mA XCV1000E 500 mA XCV1600E 500 mA XCV2000E 500 mA XCV2600E 500 mA XCV3200E 500 mA XCV50E 2 mA XCV100E 2 mA XCV200E 2 mA XCV300E 2 mA XCV400E 2 mA XCV600E 2 mA XCV1000E 2 mA XCV1600E 2 mA XCV2000E 2 mA XCV2600E 2 mA XCV3200E 2 mA μA All –10 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Power-On Power Supply Requirements Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual current consumed depends on the power-on ramp rate of the power ...
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Input/Output Standard V, Min V, Max CTT – 0.5 V REF AGP – 0.5 V REF Notes and V for lower drive currents are sample tested Tested according to the relevant specifications. ...
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... XCV1000E 0.55 XCV1600E 0.55 XCV2000E 0.55 XCV2600E 0.55 XCV3200E 0.55 T All 0.8 IOPLI T XCV50E 1.31 IOPLID XCV100E 1.31 XCV200E 1.39 XCV300E 1.39 XCV400E 1.43 XCV600E 1.55 XCV1000E 1.55 XCV1600E 1.59 XCV2000E 1.59 XCV2600E 1.59 XCV3200E 1.59 www.xilinx.com 1-800-255-7778 2. For other standards, adjust the delays with the 8 ...
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... Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device Min T All 0. 0. 0.18 IOCKIQ T / IOPICK All 0. IOICKP T / XCV50E 1. IOPICKD T IOICKPD XCV100E 1. XCV200E 1. XCV300E 1. XCV400E 1. XCV600E 1. XCV1000E 1. XCV1600E 1. XCV2000E 1. XCV2600E 1. XCV3200E 1. All 0.28 / IOICECK T 0.0 IOCKICE T All 0.38 IOSRCKI T All 0 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Input Switching Characteristics Standard Adjustments Description Data Input Delay Adjustments Standard-specific data input delay adjustments Notes: 1. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see ...
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R IOB Output Switching Characteristics, Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in (2) Description Propagation Delays O input ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays IOB Output Switching Characteristics Standard Adjustments Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays by the values ...
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R Calculation Function of Capacitance ioop T is the propagation delay from the O Input of the IOB to ioop the pad. The values for T are based on the standard ioop capacitive load (C ) ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Clock Distribution Switching Characteristics Description GCLK IOB and Buffer Global Clock PAD to output. Global Clock Buffer I input to O output I/O Standard Global Clock Input Adjustments Description Data Input Delay Adjustments ...
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R CLB Switching Characteristics Delays originating at F/G inputs vary slightly according to the input used, see worst-case. Precise values are provided by the timing analyzer. Description Combinatorial Delays 4-input function: F/G inputs to X/Y outputs 5-input function: F/G inputs ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays F5IN CLK CE Module COUT LUT ...
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R CLB Arithmetic Switching Characteristics Setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. Precise values are provided by the timing analyzer. Description Combinatorial Delays F operand inputs to X ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode Shift-Register Mode Clock ...
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R Block RAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK Minimum Pulse Width, High Minimum Pulse Width, Low ...
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... DLL output jitter is already included in the timing calculation. Module Symbol Device T XCV50E ICKOFDLL XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www.xilinx.com 1-800-255-7778 ...
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... DS022-3 (v2.9.2) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device T XCV50E ICKOF XCV100E IOB XCV200E XCV300E XCV400E XCV600E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E threshold with 35 pF external capacitive load. For other I/O standards and different loads, see CC www ...
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... PSDLL PHDLL XCV100E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV200E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV300E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV400E 1.5 / –0.4 1.5 / –0.4 1.6 / –0.4 1.7 / –0.4 XCV600E 1.5 / – ...
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... DS022-3 (v2.9.2) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Symbol Device Min IOB Input Switching XCV50E 1 PSFD PHFD XCV100E 1 XCV200E 1 XCV300E 2 XCV400E 2 XCV600E 2 XCV1000E 2 XCV1600E 2 XCV2000E 2 XCV2600E 2 XCV3200E 2 ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays DLL Timing Parameters All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect ...
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R DLL Clock Tolerance, Jitter, and Phase Information All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. Description Input Clock Period Tolerance Input Clock Jitter Tolerance ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Revision History The following table shows the revision history for this document. Date Version 12/7/99 1.0 Initial Xilinx release. 1/10/00 1.1 Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL, Select ...
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R Date Version • Under 07/23/01 2.2 • Changes made to SSTL symbol names in Standard Adjustments • Removed T 07/26/01 2.3 • Reworded power supplies footnote to 9/18/01 2.4 • Updated the speed grade designations used in data sheets, ...
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Virtex™-E 1.8 V Field Programmable Gate Arrays Module www.xilinx.com 1-800-255-7778 R DS022-3 (v2.9.2) March 14, 2003 Production Product Specification ...
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R DS022-4 (v2.5) March 14, 2003 Virtex-E Pin Definitions Pin Name Dedicated Pin GCK0, GCK1, Yes GCK2, GCK3 M0, M1, M2 Yes CCLK Yes PROGRAM Yes DONE Yes INIT No BUSY/DOUT No D0/DIN, No D1, D2, D3, D4, D5, D6, ...
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... Table 1. XCV200E Device, FG456 Package The Virtex-E XCV200E has two I/O pins swapped with the Virtex XCV200 to accommodate differential clock pairing. XCV400E Device, FG676 Package The Virtex-E XCV400E has two I/O pins swapped with the Virtex XCV400 to accommodate differential clock pairing. ...
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R Low Voltage Differential Signals The Virtex-E family incorporates low-voltage signalling (LVDS and LVPECL). Two pins are utilized for these signals to be connected to a Virtex-E device. These are known as differential pin pairs. Each differential pin pair has ...
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... Bank Pin Description 0 GCK3 IO_VREF_L0N_YY 0 IO_L0P_YY 0 IO_L1N_YY 0 IO_L1P_YY 0 IO_LVDS_DLL_L2N 0 IO_VREF 0 IO_VREF 0 IO_VREF 1 GCK2 IO_LVDS_DLL_L2P 1 IO_L3N_YY 1 IO_L3P_YY 1 IO_L4N_YY 1 IO_VREF_L4P_YY 1 IO_WRITE_L5N_YY 1 IO_CS_L5P_YY Module Table 4: CS144 — XCV50E, XCV100E, XCV200E Bank Pins CCO A2, A13 B12, G11, M13 2 N1, N7, N13 2 B2, G2 Table 5 is Differential Pin # ...
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... IO 6 IO_L25P 6 IO_VREF_L25N 6 IO_L24P_YY 6 IO_L24N_YY 6 IO_L23P 6 IO_VREF_L23N 6 IO_VREF 6 IO_VREF 6 IO_L22N_YY 6 IO_L22P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 4: CS144 — XCV50E, XCV100E, XCV200E Pin # Bank Pin Description M11 6 L11 N10 IO_VREF_L27P L10 7 IO_L28N_YY ...
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... GND NA GND NA GND NA GND NA GND Notes I/O option only in the XCV200E; otherwise, I/O REF option only I/O option only in the XCV100E, 200E; otherwise, REF I/O option only. Module CS144 Differential Pin Pairs Pin # Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ ...
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... P230 IO 1 P229 IO_VREF_L2N_YY P228 IO_L2P_YY P224 IO_L3N_YY P223 IO_L3P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Other Pin # AO Functions P222 NA IO_LVDS_DLL P221 √ - P220 √ ...
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... P139 IO_L26P_YY P138 IO_D5_L26N_YY P134 IO_D6_L27P_Y 1 P133 IO_VREF_L27N_Y P132 IO P131 IO_L28P_Y P130 IO_VREF_L28N_Y P128 IO_L29P_Y P127 IO_L29N_Y 2 P126 IO_VREF_L30P_Y Module Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Bank Pin # 2 P125 2 P124 2 P123 IO_INIT_L31N_YY 2 2 P118 2 P117 2 2 P115 2 P114 2 P113 2 ...
Page 95
... IO_L54P_Y P34 IO_L55N_Y 3 P33 IO_VREF_L55P_Y P31 IO P28 IO_L56N_YY P27 IO_L56P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 6: PQ240 — XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Bank Pin # 3 5 P26 5 P24 5 P23 IO_VREF_L57P_Y 5 P21 5 P20 ...
Page 96
... Notes I/O option only in the XCV100E, 200E, 300E, 400E; REF 7 otherwise, I/O option only I/O option only in the XCV200E, 300E, 400E; REF otherwise, I/O option only I/O option only in the XCV400E; otherwise, I/O NA REF option only. NA www.xilinx.com 1-800-255-7778 R Pin Description Bank ...
Page 97
... P188 P189 13 1 P186 P187 14 1 P184 P185 15 2 P178 P177 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 7: PQ240 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pair Other 24 AO Functions IO_DLL_L40P ...
Page 98
... Virtex™-E 1.8 V Field Programmable Gate Arrays Table 7: PQ240 Differential Pin Pair Summary XCV50E, XCV100E, XCV200E, XCV300E, XCV400E Pair Bank P Pin N Pin 48 6 P56 P57 49 6 P52 P53 50 6 P49 P50 51 6 P46 P47 52 6 P41 P42 53 6 P38 P39 54 6 P35 ...
Page 99
R Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P210 GCK2 P209 IO_LVDS_DLL_L6P P208 IO_VREF P207 VCCO P206 IO_L7N_Y P205 IO_VREF_L7P_Y P204 GND P203 IO_L8N_Y P202 IO_L8P_Y 1 P201 IO_VREF P200 IO_L9N_YY P199 IO_L9P_YY P198 VCCINT P197 VCCO ...
Page 100
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P138 IO_D5_L26N_YY P137 VCCINT P136 VCCO P135 GND P134 IO_D6_L27P_Y P133 IO_VREF_L27N_Y P132 IO_VREF P131 IO_L28P_Y P130 IO_VREF_L28N_Y P129 GND P128 IO_L29P_Y P127 ...
Page 101
R Table 8: HQ240 — XCV600E, XCV1000E Pin # Pin Description P66 IO_VREF_L46P P65 IO_L46N P64 IO_L47P_YY P63 IO_L47N_YY P62 M2 P61 VCCO P60 M0 P59 GND P58 M1 P57 IO_L48N_YY P56 IO_L48P_YY P55 VCCO P54 IO_VREF P53 IO_L49N_Y P52 ...
Page 102
Virtex™-E 1.8 V Field Programmable Gate Arrays HQ240 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...
Page 103
... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays BG352 Ball Grid Array Packages XCV100E, XCV200E, and XCV300E devices in BG352 Ball Other Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless ...
Page 104
... IO_L14N_YY 1 IO_L14P_YY 1 IO_L15N_YY 1 IO_VREF_1_L15P_YY 1 IO_L16N _Y 1 IO_L16P IO_L17N_YY 1 IO_VREF_1_L17P_YY 1 IO_L18N_YY 1 IO_L18P_YY IO_L19N_YY 1 IO_VREF_1_L19P_YY Module Table 10: BG352 — XCV100E, XCV200E, XCV300E Pin # Bank Pin Description C15 1 1 B15 1 A15 1 D14 1 IO_WRITE_L20N_YY 1 IO_CS_L20P_YY B14 A13 2 IO_DOUT_BUSY_L21P_YY 1 B13 2 IO_DIN_D0_L21N_YY C13 2 A12 2 B12 2 C12 2 IO_VREF_2_L22P_YY ...
Page 105
... IO_D6_L38P _Y 3 IO_VREF_3_L38N _Y 3 IO_L39P _Y 3 IO_L39N IO_L40P_Y 3 IO_VREF_3_L40N_Y 3 IO_L41P_YY 3 IO_L41N_YY IO_L42P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Pin # Bank Pin Description M3 3 IO_VREF_3_L42N_YY IO_D7_L43P_YY N2 3 IO_INIT_L43N_YY ...
Page 106
... IO 5 IO_L59P_YY 5 IO_L59N_YY 5 IO_L60P_YY 5 IO_VREF_5_L60N_YY 5 IO_L61P _Y 5 IO_L61N IO_L62P_YY 5 IO_VREF_5_L62N_YY 5 IO_L63P_YY 5 IO_L63N_YY 5 IO Module Table 10: BG352 — XCV100E, XCV200E, XCV300E Pin # Bank Pin Description AC12 5 AD12 5 IO_VREF_5_L64N_YY AE12 5 AF12 5 1 AD13 5 AC13 AE13 6 6 AF14 6 AD14 6 1 AF15 6 AE15 6 IO_VREF_6_L66N_YY AD15 ...
Page 107
... IO_L83P IO_L84N_Y 7 IO_VREF_7_L84P_Y 7 IO_L85N_YY 7 IO_L85P_YY IO_L86N_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 10: BG352 — XCV100E, XCV200E, XCV300E Pin # Bank Pin Description R25 7 IO_VREF_7_L86P_YY R26 7 P24 7 1 P23 7 N26 7 N25 NA N24 NA 1 M26 ...
Page 108
... NA AF17 NA AC20 NA AC14 NA AE25 NA W23 NA U26 NA N23 NA K26 NA G23 Notes Connect in the XCV100E I/O option only in the XCV200E and XCV300E; REF otherwise, I/O option only. A26 A25 A22 www.xilinx.com 1-800-255-7778 R Pin # GND A19 GND A14 GND A8 GND A5 GND A2 GND A1 GND B26 ...
Page 109
... B11 A11 13 1 D11 C11 14 1 C10 DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 11: BG352 Differential Pin Pair Summary XCV100E, XCV200E, XCV300E Pair Other 27 AO Functions LVDS LVDS LVDS LVDS √ VREF_0 36 √ ...
Page 110
... F24 E25 86 7 E24 D25 Notes the XCV100E the XCV200E. Module BG432 Ball Grid Array Packages XCV300E, XCV400E, and XCV600E devices in BG432 Ball Other Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless AO Functions device-dependent as indicated in the footnotes. If the pin is √ ...
Page 111
R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 0 IO_L12N_YY 0 IO_L12P_YY 0 IO_VREF_L13N_YY 0 IO_L13P_YY 0 IO_L14N_Y 0 IO_L14P_Y 0 IO_VREF_L15N_Y 0 IO_L15P_Y 0 IO_LVDS_DLL_L16N 1 GCK2 ...
Page 112
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 2 IO_L41N_Y 2 IO_VREF_L42P_Y 2 IO_L42N_Y 2 IO_VREF_L43P_YY 2 IO_D1_L43N_YY 2 IO_D2_L44P_YY 2 IO_L44N_YY 2 IO_L45P_Y 2 IO_L45N_Y 2 IO_L46P_Y 2 IO_L46N_Y 2 ...
Page 113
R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 4 IO_L70N_Y 4 IO_L71P_YY 4 IO_L71N_YY 4 IO_VREF_L72P_YY 4 IO_L72N_YY 4 IO_L73P_Y 4 IO_L73N_Y 4 IO_L74P_YY 4 IO_L74N_YY 4 IO_VREF_L75P_YY 4 IO_L75N_YY 4 IO_L76P_Y 4 IO_L76N_Y 4 IO_VREF_L77P_Y 4 ...
Page 114
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description IO_L103N_YY 6 IO_L103P_YY 6 IO_L104N 6 IO_L104P 6 IO_L105N_Y 6 IO_L105P_Y 6 ...
Page 115
R Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 7 IO_L132P_Y 7 IO_L133N 7 IO_L133P 7 IO_L134N_Y 7 IO_VREF_L134P_Y 7 IO_L135N_Y 7 IO_L135P_Y 7 IO_L136N 7 IO_L136P 2 CCLK 3 DONE NA DXN NA DXP ...
Page 116
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 12: BG432 — XCV300E, XCV400E, XCV600E Bank Pin Description 6 VCCO 7 VCCO 7 VCCO 7 VCCO NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 117
R BG432 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also Vir- tex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO ...
Page 118
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 13: BG432 Differential Pin Pair Summary XCV300E, XCV400E, XC600E Pair Bank P N Pin Pin ...
Page 119
R Table 13: BG432 Differential Pin Pair Summary XCV300E, XCV400E, XC600E Pair Bank P N Pin Pin 112 6 AB29 AB28 113 6 AA29 AB31 114 6 Y29 Y28 115 6 Y31 Y30 116 6 W30 W29 117 6 V29 ...
Page 120
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 0 IO_L11P_YY 0 IO_L12N_Y 0 IO_L12P_Y 0 IO_L13N_YY 0 IO_L13P_YY 0 IO_VREF_L14N_YY 0 IO_L14P_YY 0 IO_L15N_Y 0 IO_L15P_Y 0 IO_L16N_YY 0 ...
Page 121
R Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 1 IO_L43N_Y 1 IO_VREF_L43P_Y 1 IO_WRITE_L44N_YY 1 IO_CS_L44P_YY IO_DOUT_BUSY_L45P_YY 2 IO_DIN_D0_L45N_YY 2 IO_L46P_Y 2 IO_VREF_L46N_Y 2 IO_L47P_Y 2 ...
Page 122
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 3 IO_D4_L73P_YY 3 IO_VREF_L73N_YY 3 IO_L74P_Y 3 IO_L74N_Y 3 IO_L75P_Y 3 IO_L75N_Y 3 IO_L76P_Y 3 IO_VREF_L76N_Y 3 IO_L77P_Y 3 IO_L77N_Y 3 ...
Page 123
R Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 4 IO_L104N_YY 4 IO_L105P_Y 4 IO_L105N_Y 4 IO_L106P_YY 4 IO_L106N_YY 4 IO_VREF_L107P_YY 4 IO_L107N_YY 4 IO_L108P_Y 4 IO_L108N_Y 4 IO_L109P_YY 4 IO_L109N_YY 4 IO_VREF_L110P_YY 4 IO_L110N_YY 4 ...
Page 124
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 5 IO_L136P_Y 5 IO_VREF_L136N_Y IO_L137N_YY 6 IO_L137P_YY 6 IO_L138N_Y 6 IO_VREF_L138P_Y 6 ...
Page 125
R Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 7 IO_L165N_YY 7 IO_VREF_L165P_YY 7 IO_L166N_Y 7 IO_L166P_Y 7 IO_L167N_Y 7 IO_L167P_Y 7 IO_L168N_Y 7 IO_VREF_L168P_Y 7 IO_L169N_Y 7 IO_L169P_Y 7 IO_L170N_Y 7 IO_L170P_Y 7 IO_L171N_YY 7 ...
Page 126
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA ...
Page 127
R Table 14: BG560 — XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 128
Virtex™-E 1.8 V Field Programmable Gate Arrays BG560 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...
Page 129
R Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin ...
Page 130
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 15: BG560 Differential Pin Pair Summary XCV400E, XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 109 4 AJ14 AK14 110 4 AM14 AN15 111 4 AJ15 AK15 112 4 AL15 ...
Page 131
... DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays FG256 Fine-Pitch Ball Grid Array Packages XCV50E, XCV100E, XCV200E, and XCV300E devices in Other FG256 fine-pitch Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either ...
Page 132
... IO_L21N_YY 2 IO_VREF_L22P_Y 2 IO_L22N_Y 2 IO_L23P 2 IO_L23N 2 IO_VREF_L24P_Y 2 IO_D1_L24N_Y 2 IO_D2_L25P_YY 2 IO_L25N_YY 2 IO_L26P 2 IO_L26N 2 IO_L27P_YY 2 IO_L27N_YY Module Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Pin # Bank Pin Description A10 2 IO_VREF_L28P_Y D10 2 IO_D3_L28N_Y C10 2 A11 2 B11 2 1 E11 2 A12 D11 3 A13 3 C11 3 B12 3 IO_D4_L32P_Y ...
Page 133
... IO_L55P_YY 5 IO_L55N_YY 5 IO_L56P_YY 5 IO_VREF_L56N_YY 5 IO_L57P_Y 5 IO_L57N_Y 5 IO_L58P_YY DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Pin # Bank Pin Description P12 5 IO_VREF_L58N_YY 2 R13 5 N12 5 T13 5 IO_VREF_L60P_Y T12 5 P11 ...
Page 134
... IO_L76P 7 IO_L77N_YY 7 IO_L77P_YY 7 IO_L78N_Y 7 IO_VREF_L78P_Y 7 IO_L79N 7 IO_L79P 7 IO_L80N_Y 7 IO_VREF_L80P_Y 7 IO_L81N_YY 7 IO_L81P_YY 7 IO_VREF_L82N 7 IO_L82P 2 CCLK 3 DONE NA DXN NA DXP PROGRAM NA TCK NA TDI 2 TDO NA TMS NA VCCINT NA VCCINT NA VCCINT Module Table 16: FG256 Package — XCV50E, XCV100E, XCV200E, XCV300E Pin # Bank Pin Description D15 4 R14 P15 C4 ...
Page 135
... V or I/O option only in the XCV100E, 200E, 300E; REF otherwise, I/O option only I/O option only in the XCV200E, 300E; otherwise, REF I/O option only. DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays FG256 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ ...
Page 136
... VREF 79 √ √ VREF √ VREF Notes the XCV50E, 200E, 300E. √ the XCV50E, 200E the XCV50E, 300E the XCV100E, 200E. 1 VREF the XCV200E the XCV100E the XCV50E. NA IO_LVDS_DLL 1 VREF 1 - www.xilinx.com 1-800-255-7778 P N Bank Pin Pin AO Functions √ √ √ ...
Page 137
... R FG456 Fine-Pitch Ball Grid Array Packages XCV200E and XCV300E devices in FG456 fine-pitch Ball Grid Array packages have footprint compatibility. Pins labeled I0_VREF can be used as either in both devices pro- vided in this package. If the pin is not used as V used as general I/O. Immediately following Table 19 for Differential Pair information ...
Page 138
... IO_DOUT_BUSY_L29P_YY 2 IO_DIN_D0_L29N_YY 2 IO_L30P_YY 2 IO_L30N_YY 2 IO_VREF_L31P_YY 2 IO_L31N_YY 2 IO_L32P_YY 2 IO_L32N_YY 2 IO_VREF_L33P_YY 2 IO_L33N_YY 2 IO_L34P_Y 2 IO_L34N_Y 2 IO_L35P_Y 2 IO_L35N_Y 2 IO_VREF_L36P_Y 2 IO_D1_L36N_Y Module Table 18: FG456 — XCV200E and XCV300E Pin # Bank Pin Description A17 2 IO_D2_L37P_YY B17 2 A18 2 D16 2 C17 2 B18 2 A19 2 D17 2 C18 2 A20 2 IO_VREF_L41N C19 D18 2 1 ...
Page 139
... IO_L60P_YY 4 IO_L60N_YY 4 IO_L61P 4 IO_L61N 4 IO_VREF_L62P_YY 4 IO_L62N_YY 4 IO_L63P DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Pin # Bank Pin Description P19 4 P18 4 IO_VREF_L64P_YY R21 4 T22 4 R19 4 U22 4 R18 4 T21 4 IO_VREF_L67P_YY ...
Page 140
... IO_L83N_Y 5 IO_L84P_Y 5 IO_L84N_Y 5 IO_L85P_YY 5 IO_VREF_L85N_YY 5 IO_L86P_YY 5 IO_L86N_YY 5 IO_L87P_YY 5 IO_VREF_L87N_YY 5 IO_L88P_YY 5 IO_L88N_YY IO_L89N_YY 6 IO_L89P_YY Module Table 18: FG456 — XCV200E and XCV300E Pin # Bank Pin Description W11 6 V11 6 Y10 6 IO_VREF_L91N_YY AB10 6 W10 6 V10 IO_VREF_L93N_YY AB9 AA8 IO_VREF_L96N_Y W7 6 AA7 6 AB6 6 AA6 6 AB5 6 AA5 6 ...
Page 141
... IO_L112N_Y 7 IO_VREF_L112P_Y 7 IO_L113N_Y 7 IO_L113P_Y 7 IO_L114N_YY 7 IO_L114P_YY 7 IO_L115N_YY 7 IO_VREF_L115P_YY 7 IO_L116N_YY 7 IO_L116P_YY 7 IO_L117N_YY 7 IO_VREF_L117P_YY 7 IO_L118N_YY 7 IO_L118P_YY 2 CCLK 3 DONE NA DXN DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays Table 18: FG456 — XCV200E and XCV300E Pin # Bank Pin Description ...
Page 142
... VCCO_6 NA VCCO_6 NA VCCO_6 NA VCCO_6 NA VCCO_6 NA VCCO_6 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_5 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_4 NA VCCO_3 NA VCCO_3 NA VCCO_3 NA VCCO_3 NA VCCO_3 NA VCCO_3 Module Table 18: FG456 — XCV200E and XCV300E Pin # Bank Pin Description T15 NA T16 U17 V18 U10 T11 ...
Page 143
... R Table 18: FG456 — XCV200E and XCV300E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND Note the XCV200E device. ...
Page 144
... M19 M17 47 3 N22 N21 48 3 N20 N18 49 3 N19 P21 50 3 P20 P19 51 3 P18 R21 52 3 T22 R19 Module Table 19: FG456 Differential Pin Pair Summary XCV200E, XCV300E Other AO Functions Pair √ √ VREF √ VREF 59 √ √ VREF 61 √ ...
Page 145
... D2 E3 118 Notes the XCV200E the XCV300E. DS022-4 (v2.5) March 14, 2003 Production Product Specification Virtex™-E 1.8 V Field Programmable Gate Arrays FG676 Fine-Pitch Ball Grid Array Package XCV400E and XCV600E devices in the FG676 fine-pitch Ball Grid Array package have footprint compatibility. Pins ...
Page 146
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 0 IO_L9N 0 IO_L9P 0 IO_L10N 0 IO_VREF_L10P 0 IO_L11N_YY 0 IO_L11P_YY 0 IO_L12N_Y 0 IO_L12P_Y 0 IO_L13N_YY 0 IO_L13P_YY 0 IO_L14N_YY 0 IO_L14P_YY ...
Page 147
R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 1 IO_L40P_YY 1 IO_L41N_YY 1 IO_VREF_L41P_YY 1 IO_L42N_YY 1 IO_L42P_YY 1 IO_L43N_Y 1 IO_L43P_Y 1 IO_WRITE_L44N_YY 1 IO_CS_L44P_YY ...
Page 148
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description IO_L69P_YY 3 IO_L69N_YY 3 IO_L70P_Y 3 IO_VREF_L70N_Y 3 IO_L71P_Y 3 IO_L71N_Y 3 IO_L72P_YY 3 IO_L72N_YY ...
Page 149
R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 4 IO_L98N_YY 4 IO_L99P_YY 4 IO_L99N_YY 4 IO_L100P_Y 4 IO_L100N_Y 4 IO_VREF_L101P_Y 4 IO_L101N_Y 4 IO_L102P 4 IO_L102N 4 IO_L103P 4 IO_VREF_L103N 4 IO_L104P_YY 4 IO_L104N_YY 4 IO_L105P_Y 4 IO_L105N_Y ...
Page 150
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 5 IO_L129N_Y 5 IO_L130P_YY 5 IO_L130N_YY 5 IO_L131P_YY 5 IO_VREF_L131N_YY 5 IO_L132P_YY 5 IO_L132N_YY 5 IO_L133P_YY 5 IO_L133N_YY 5 IO_L134P_YY 5 IO_VREF_L134N_YY 5 IO_L135P_YY ...
Page 151
R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description IO_L160N_YY 7 IO_L160P_YY 7 IO_L161N_YY 7 IO_L161P_YY 7 IO_L162N_Y 7 IO_VREF_L162P_Y ...
Page 152
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description ...
Page 153
R Table 20: FG676 — XCV400E, XCV600E Bank Pin Description 0 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 2 VCCO 3 VCCO 3 VCCO ...
Page 154
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 20: FG676 — XCV400E, XCV600E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...
Page 155
R FG676 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the pin pair can be used as ...
Page 156
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E P N Ban Pair k Pin Pin 52 2 G24 H22 53 2 J21 G25 54 2 G26 J22 55 2 H24 J23 56 ...
Page 157
R Table 21: FG676 Differential Pin Pair Summary XCV400E, XCV600E P N Ban Pair k Pin Pin 120 5 AD11 Y12 121 5 AB11 AD10 122 5 AC11 AE10 123 5 AC10 AA11 124 5 Y11 AD9 125 5 AB10 ...
Page 158
Virtex™-E 1.8 V Field Programmable Gate Arrays FG680 Fine-Pitch Ball Grid Array Package XCV600E, XCV1000E, XCV1600E, devices in the FG680 fine-pitch Ball Grid Array package have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts unless ...
Page 159
R Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description IO_LVDS_DLL_L29P 1 IO_L30N_Y 1 IO_VREF_L30P_Y 1 IO_L31N_Y 1 IO_L31P_Y 1 IO_L32N_YY 1 IO_VREF_L32P_YY 1 IO_L33N_YY 1 IO_L33P_YY 1 IO_L34N_Y 1 IO_L34P_Y 1 IO_L35N_Y 1 IO_L35P_Y ...
Page 160
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 2 IO_L63N 2 IO_L64P 2 IO_L64N 2 IO_VREF_L65P_Y 2 IO_L65N_Y 2 IO_L66P_YY 2 IO_L66N_YY 2 IO_L67P 2 IO_L67N 2 IO_L68P_Y 2 IO_L68N_Y ...
Page 161
R Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 3 IO_L97N 3 IO_L98P_YY 3 IO_L98N_YY 3 IO_D4_L99P_YY 3 IO_VREF_L99N_YY 3 IO_L100P_Y 3 IO_L100N_Y 3 IO_L101P 3 IO_L101N 3 IO_L102P_YY 3 IO_L102N_YY 3 IO_L103P_Y 3 IO_VREF_L103N_Y 3 IO_L104P ...
Page 162
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 4 IO_VREF_L132P_YY 4 IO_L132N_YY 4 IO_L133P_Y 4 IO_L133N_Y 4 IO_VREF_L134P_Y 4 IO_L134N_Y 4 IO_L135P_YY 4 IO_L135N_YY 4 IO_VREF_L136P_YY 4 IO_L136N_YY 4 IO_L137P_Y ...
Page 163
R Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 5 IO_L166P_YY 5 IO_L166N_YY 5 IO_L167P_Y 5 IO_L167N_Y 5 IO_L168P_Y 5 IO_L168N_Y 5 IO_L169P_YY 5 IO_L169N_YY 5 IO_L170P_YY 5 IO_VREF_L170N_YY 5 IO_L171P_Y 5 IO_L171N_Y 5 IO_L172P_Y 5 IO_L172N_Y ...
Page 164
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 6 IO_VREF_L200N_YY 6 IO_L200P_YY 6 IO_L201N_YY 6 IO_L201P_YY 6 IO_L202N_Y 6 IO_L202P_Y 6 IO_L203N 6 IO_L203P 6 IO_L204N 6 IO_L204P 6 IO_VREF_L205N_Y ...
Page 165
R Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 7 IO_L234N_YY 7 IO_L234P_YY 7 IO_L235N_YY 7 IO_VREF_L235P_YY 7 IO_L236N 7 IO_L236P 7 IO_L237N 7 IO_VREF_L237P 7 IO_L238N_YY 7 IO_L238P_YY 7 IO_L239N_YY 7 IO_VREF_L239P_YY 7 IO_L240N_Y 7 IO_L240P_Y ...
Page 166
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description 0 VCCO 0 VCCO 0 VCCO 0 VCCO 0 VCCO 0 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO 1 VCCO ...
Page 167
R Table 22: FG680 - XCV600E, XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND ...
Page 168
Virtex™-E 1.8 V Field Programmable Gate Arrays FG680 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...
Page 169
R Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin ...
Page 170
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin AO 120 3 AN4 AT1 121 3 AR2 AP4 122 3 AT2 AR3 123 3 AR4 ...
Page 171
R Table 23: FG680 Differential Pin Pair Summary XCV600E, XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin AO 188 6 AP39 AP38 189 6 AN38 AN36 190 6 AN39 AN37 191 6 AM38 AM36 192 6 AL36 AM37 193 ...
Page 172
Virtex™-E 1.8 V Field Programmable Gate Arrays FG860 Fine-Pitch Ball Grid Array Package XCV1000E, XCV1600E, and XCV2000E devices in the FG680 fine-pitch Ball Grid Array package have footprint compatibility. Pins labeled I0_VREF can be used as either in all parts ...
Page 173
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 0 IO_VREF_L27N_YY 0 IO_L27P_YY 0 IO_L28N_Y 0 IO_L28P_Y 0 IO_L29N_Y 0 IO_L29P_Y 0 IO_L30N_YY 0 IO_L30P_YY 0 IO_VREF_L31N_YY 0 IO_L31P_YY 0 IO_L32N_Y 0 IO_L32P_Y 0 IO_VREF_L33N_Y 0 IO_L33P_Y 0 ...
Page 174
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 1 IO_L57N_Y 1 IO_VREF_L57P_Y 1 IO_L58N_Y 1 IO_L58P_Y 1 IO_L59N_YY 1 IO_VREF_L59P_YY 1 IO_L60N_YY 1 IO_L60P_YY 1 IO_L61N_Y 1 IO_L61P_Y 1 IO_L62N_Y 1 ...
Page 175
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 2 IO_D1_L87N_YY 2 IO_D2_L88P_YY 2 IO_L88N_YY 2 IO_L89P_Y 2 IO_L89N_Y 2 IO_L90P_Y 2 IO_L90N_Y 2 IO_L91P_Y 2 IO_L91N_Y 2 IO_L92P 2 IO_L92N 2 IO_L93P_Y 2 IO_L93N_Y 2 IO_VREF_L94P_Y 2 ...
Page 176
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 3 IO_L117N_Y 3 IO_L118P 3 IO_L118N 3 IO_L119P_Y 3 IO_L119N_Y 3 IO_L120P_Y 3 IO_L120N_Y 3 IO_L121P_Y 3 IO_L121N_Y 3 IO_L122P_YY 3 IO_D5_L122N_YY 3 ...
Page 177
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 4 IO_L147N_YY 4 IO_L148P_Y 4 IO_L148N_Y 4 IO_L149P_Y 4 IO_L149N_Y 4 IO_L150P_YY 4 IO_L150N_YY 4 IO_VREF_L151P_YY 4 IO_L151N_YY 4 IO_L152P_Y 4 IO_L152N_Y 4 IO_VREF_L153P_Y 4 IO_L153N_Y 4 IO_L154P_YY 4 ...
Page 178
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 5 IO_L178P_Y 5 IO_L178N_Y 5 IO_L179P_YY 5 IO_VREF_L179N_YY 5 IO_L180P_YY 5 IO_L180N_YY 5 IO_L181P_Y 5 IO_L181N_Y 5 IO_L182P_Y 5 IO_L182N_Y 5 IO_L183P_YY 5 ...
Page 179
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description IO_L211N_YY 6 IO_L211P_YY 6 IO_L212N_Y 6 IO_L212P_Y 6 IO_L213N_Y 6 IO_L213P_Y 6 IO_VREF_L214N_Y 6 IO_L214P_Y 6 ...
Page 180
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 6 IO_VREF_L245N_Y 6 IO_L245P_Y ...
Page 181
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description 7 IO_L275N_Y 7 IO_VREF_L275P_Y 7 IO_L276N_Y 7 IO_L276P_Y 7 IO_L277N 7 IO_L277P 7 IO_L278N_Y 7 IO_VREF_L278P_Y 7 IO_L279N_Y 7 IO_L279P_Y 7 IO_L280N_Y 7 IO_L280P_Y 2 CCLK 3 DONE NA ...
Page 182
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA ...
Page 183
R Table 24: FG860 — XCV1000E, XCV1600E, XCV2000E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 184
Virtex™-E 1.8 V Field Programmable Gate Arrays FG860 Differential Pin Pairs Virtex-E devices have differential pin pairs that can also pro- vide other functions when not used as a differential pair. A √ in the AO column indicates that the ...
Page 185
R Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 52 1 D11 B15 53 1 C14 E11 54 1 B14 C10 55 1 E10 A13 C13 57 1 A12 ...
Page 186
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 120 3 AH1 AL5 121 3 AH2 AM4 122 3 AH3 AM5 123 3 AJ1 AN3 124 ...
Page 187
R Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 188 5 AY27 AV28 189 5 BA27 AW29 190 5 BB28 AV29 191 5 AY28 AW30 192 5 BA28 AW31 193 5 BB29 ...
Page 188
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 25: FG860 Differential Pin Pair Summary XCV1000E, XCV1600E, XCV2000E P N Pair Bank Pin Pin 256 7 T38 T41 257 7 T42 R39 258 7 R38 R42 259 7 P39 R40 260 ...
Page 189
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 0 IO_L6N_Y 0 IO_L6P_Y 0 IO_L7N_Y 0 IO_L7P_Y 0 IO_L8N_YY 0 IO_L8P_YY 0 IO_VREF_L9N_YY 0 IO_L9P_YY 0 IO_L10N_Y 0 IO_L10P_Y 0 IO_L11N_Y 0 IO_L11P_Y 0 IO_L12N_YY 0 IO_L12P_YY 0 ...
Page 190
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description IO_LVDS_DLL_L34P 1 IO_L35N_YY 1 IO_VREF_L35P_YY 1 IO_L36N_YY 1 IO_L36P_YY 1 IO_L37N_YY 1 IO_VREF_L37P_YY 1 IO_L38N_YY 1 IO_L38P_YY 1 ...
Page 191
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description ...
Page 192
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 2 IO_L99P_YY 2 IO_L99N_YY 2 IO_L100P 2 IO_L100N 2 IO_L101P_YY 2 IO_L101N_YY 2 IO_VREF_L102P_YY 2 IO_L102N_YY 2 IO_L103P_YY 2 IO_L103N_YY 2 IO_VREF_L104P_YY 2 ...
Page 193
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 3 IO_L127P_YY 3 IO_VREF_L127N_YY 3 IO_L128P_YY 3 IO_L128N_YY 3 IO_L129P 3 IO_L129N 3 IO_L130P_YY 3 IO_L130N_YY 3 IO_L131P_YY 3 IO_VREF_L131N_YY 3 IO_L132P 3 IO_L132N 3 IO_L133P_YY 3 IO_L133N_YY 3 ...
Page 194
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 4 IO_L154N 4 IO_L155P_YY 4 IO_L155N_YY 4 IO_VREF_L156P_YY 4 IO_L156N_YY 4 IO_L157P 4 IO_L157N 4 IO_L158P_YY 4 IO_L158N_YY 4 IO_L159P 4 IO_VREF_L159N 4 ...
Page 195
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 5 IO_L182N 5 IO_L183P 5 IO_L183N 5 IO_L184P_YY 5 IO_VREF_L184N_YY 5 IO_L185P_YY 5 IO_L185N_YY 5 IO_L186P 5 IO_L186N 5 IO_L187P 5 IO_L187N 5 IO_L188P_YY 5 IO_VREF_L188N_YY 5 IO_L189P_YY 5 ...
Page 196
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description IO_L212N_YY 6 IO_L212P_YY 6 IO_L213N 6 IO_L213P 6 IO_L214N 6 IO_L214P 6 IO_VREF_L215N_YY 6 IO_L215P_YY 6 ...
Page 197
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description ...
Page 198
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description 7 IO_L275N_YY 7 IO_L275P_YY 7 IO_L276N_YY 7 IO_L276P_YY 7 IO_L277N 7 IO_VREF_L277P 7 IO_L278N_YY 7 IO_L278P_YY 7 IO_L279N_Y 7 IO_L279P_Y 7 IO_L280N_YY 7 ...
Page 199
R Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description NA VCCO_0 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_1 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA VCCO_2 NA ...
Page 200
Virtex™-E 1.8 V Field Programmable Gate Arrays Table 26: FG900 — XCV600E, XCV1000E, XCV1600E Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...