XC5VLX50-3FFG324C Xilinx Inc, XC5VLX50-3FFG324C Datasheet - Page 221

IC FPGA VIRTEX-5 50K 324FBGA

XC5VLX50-3FFG324C

Manufacturer Part Number
XC5VLX50-3FFG324C
Description
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr

Specifications of XC5VLX50-3FFG324C

Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

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Quantity
Price
Part Number:
XC5VLX50-3FFG324C
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Quantity:
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Part Number:
XC5VLX50-3FFG324C
Manufacturer:
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Quantity:
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Part Number:
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0
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
without connecting the VRN/VRP pins on these banks to external resistors. DCI
impedance control in cascaded banks is received from the master bank.
When using DCI cascading, the DCI control circuitry in the master bank creates and routes
DCI control to the cascaded banks in daisy-chain style. Only the master bank’s VRN/VRP
pins are required when using DCI cascading.
Also, when using DCI cascading, only one set of VRN/VRP pins provides the DCI
reference voltage for multiple banks. DCI cascading:
Similarly, due to the center column architecture, the half-size banks 1, 2, 3, and 4 are
separated from all the other banks in the center column by the CMT tiles. It is not possible
to cascade across the CMT tiles. This affects the larger devices that have more than four
user I/O center column banks (plus bank 0). For instance, bank 4 cannot be cascaded with
bank 6, and bank 3 cannot be cascaded with bank 5. Bank 3 can only be cascaded with bank
1, and bank 4 can only be cascaded with bank 2.
Figure 6-5
Reduces overall power, since fewer voltage references are required
Frees up VRN/VRP pins on slave banks for general customer use
DCI in banks 1 and 2 is supported only through cascading. These two banks do not
have VRN/VRP pins and therefore cannot be used as master or stand-alone DCI
banks. Cascading is not possible through bank 0.
shows DCI cascading support over multiple banks. Bank B is the master bank.
www.xilinx.com
SelectIO Resources General Guidelines
221

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