XC5VLX50T-3FF665C Xilinx Inc, XC5VLX50T-3FF665C Datasheet - Page 4

• Manufacturer Part Number: XC5VLX50T-3FF665C
• Description: IC FPGA VIRTEX-5 50K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-3FF665C

• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 Family Overview
Digitally Controlled Impedance (DCI)
Active I/O Termination
•
•
•
Configuration
•
•
•
•
•
•
Advanced Flip-Chip Packaging
•
•
•
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
•
•
•
•
•
•
•
•
•
•
4
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
−
−
Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
Bitstream support with dedicated fallback
reconfiguration logic
256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
Improved bitstream error detection/correction capability
Auto bus width detection capability
Partial Reconfiguration via ICAP port
Pre-engineered packaging technology for proven
superior signal integrity
−
−
Reduces SSO induced noise by up to 7x
Pb-Free and standard packages
Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
Compliant with the PCI Express Base Specification 1.1
PCI Express Endpoint block or Legacy PCI Express
Endpoint block
x8, x4, or x1 lane width
Power management support
Block RAMs used for buffering
Fully buffered transmit and receive
Management interface to access PCI Express
configuration space and internal configuration
Supports the full range of maximum payload sizes
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
Minimized inductive loops from signal to return
Optimal signal-to-PWR/GND ratios
www.xilinx.com
System Monitor
•
•
•
•
•
•
•
65-nm Copper CMOS Process
•
•
•
Tri-Mode Ethernet Media Access Controller
•
•
•
•
•
•
•
•
•
•
•
•
•
On-Chip temperature measurement (±4°C)
On-Chip power supply measurement (±1%)
Easy to use, self-contained
−
−
−
User accessible 10-bit 200kSPS ADC
−
−
Up to 17 external analog input channels supported
−
−
−
Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
1.0V Core Voltage
12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
Triple-oxide technology for proven reduced static power
consumption
Designed to the IEEE 802.3-2002 specification
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-negotiation
Receive address filter (5 address entries)
Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
Receive and transmit statistics available through
separate interface
Separate host and client interfaces
Support for jumbo frames
Support for VLAN
Flexible, user-configurable host interface
Supports IEEE 802.3ah-2004 unidirectional mode
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
DS100 (v5.0) February 6, 2009
Product Specification
R