XCV600-4BG432I Xilinx Inc, XCV600-4BG432I Datasheet - Page 44

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XCV600-4BG432I

Manufacturer Part Number
XCV600-4BG432I
Description
IC FPGA 2.5V I-TEMP 432-MBGA
Manufacturer
Xilinx Inc
Series
Virtex™r
Datasheet

Specifications of XCV600-4BG432I

Number Of Logic Elements/cells
15552
Number Of Labs/clbs
3456
Total Ram Bits
98304
Number Of I /o
316
Number Of Gates
661111
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
432-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Virtex™ 2.5 V Field Programmable Gate Arrays
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Module 3 of 4
20
Notes: Notes:
1.
2.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard.
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
Full Delay
Global Clock and IFF, without
DLL
IFF = Input Flip-Flop or Latch
Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Description
T
PSFD
Symbol
/T
PHFD
www.xilinx.com
1-800-255-7778
XCV1000
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
Device
XCV50
0.6 / 0
0.6 / 0
0.6 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
0.7 / 0
Min
2.3 / 0
2.3 / 0
2.4 / 0
2.5 / 0
2.5 / 0
2.6 / 0
2.6 / 0
2.7 / 0
2.8 / 0
Speed Grade
-6
(2)
For data input with different
DS003-3 (v3.2) September 10, 2002
Production Product Specification
2.6 / 0
2.6 / 0
2.7 / 0
2.8 / 0
2.8 / 0
2.9 / 0
2.9 / 0
3.1 / 0
3.1 / 0
-5
2.9 / 0
3.0 / 0
3.1 / 0
3.2 / 0
3.2 / 0
3.3 / 0
3.3 / 0
3.5 / 0
3.6 / 0
-4
Units
min
min
min
min
min
min
min
min
min
ns,
ns,
ns,
ns,
ns,
ns,
ns,
ns,
ns,
R

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