IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part NumberXC5VSX50T-2FF665C
DescriptionIC FPGA VIRTEX-5 50K 665FCBGA
ManufacturerXilinx Inc
SeriesVirtex™-5 SXT
XC5VSX50T-2FF665C datasheets
Product Change Notification
 


Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells52224Number Of Labs/clbs4080
Total Ram Bits4866048Number Of I /o360
Voltage - Supply0.95 V ~ 1.05 VMounting TypeSurface Mount
Operating Temperature0°C ~ 85°CPackage / Case665-BBGA, FCBGA
For Use WithHW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5Lead Free Status / RoHS StatusContains lead / RoHS non-compliant
Number Of Gates-  
1
Page 1
2
Page 2
3
Page 3
Page 1/3

Download datasheet (68Kb)Embed
Next
XCN07026 (v1.0.3) July 29, 2009
Overview
The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select
Virtex®-5 LXT and SXT FPGA devices.
Description
This notification includes the following changes to be implemented:
Introduction of Step 1: Specific LXT and SXT devices will begin transitioning to a new mask revision, designated as
Step 1, which will improve the CDM ESD performance. The current production silicon is designated as Step 0. The
Step 1 devices are form, fit, function, and bitstream compatible with Step 0. (For information on the Xilinx Stepping
Methodology, see
Xilinx Answer
Package change: LXT and SXT devices in packages greater than 1000 pins will begin transitioning to 10-layer
package substrates, as part of the Xilinx material standardization for the Virtex-5 FPGA family. This change is
backward-compatible with current production devices. This change will not affect the current package outline drawing.
Key Dates and Ordering Information
Key dates for this notice are detailed in Key Dates for Package Transition.
Table 1: Key Dates for Package Transition
Notification Date
December 31, 2007
If a qualification of the new material is necessary, customers can order samples of Step 1 10-layer devices by appending "S1" to the end of
*
standard part numbers from January 1, 2008 through April 30, 2008.
Starting from May 1, 2008, orders using standard part numbers will receive devices in either Step 0 or Step 1, 8-layer or 10-layer.
**
© Copyright 2007 - 2009 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands
included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.
XCN07026 (v1.0.3) July 29, 2009
Transition to Step 1 and New
Package Substrate for Select
Virtex-5 LXT and SXT FPGA
Devices
20947).
Transition Period*
January 1, 2008 - April 30, 2008
www.xilinx.com
Product/Process Change Notice
Implementation Date**
(Cross-shipping starts)
May 1, 2008
1

XC5VSX50T-2FF665C Summary of contents

  • Page 1

    XCN07026 (v1.0.3) July 29, 2009 Overview The purpose of this notification is to communicate a transition to Step 1 and a 10-layer package substrate for select Virtex®-5 LXT and SXT FPGA devices. Description This notification includes the following changes to ...

  • Page 2

    ... XC5VSX50T-FF(G)1136 XC5VSX95T-FF(G)1136 XC5VLX30T-FF(G)665 XC5VLX50T-FF(G)665 Yes XC5VSX50T-FF(G)665 Traceability Step 1 10-layer devices can be ordered by appending "S1" to the end of the standard part number. Standard ordering part numbers may be fulfilled with either 8-layer or 10-layer substrates. The top mark facilitates traceability. Step 1 devices can be visually identified by the additional "1" at the end of the third line of the package top mark (see Example Top Mark) ...

  • Page 3

    Response Note: In accordance with JESD46-C, this change is deemed accepted by the customer if no acknowledgement is received within 30 days from this notice. No response is required by this notice. For additional information or questions, please contact Important ...