XC5VLX110T-1FF1738C Xilinx Inc, XC5VLX110T-1FF1738C Datasheet - Page 306

• Manufacturer Part Number: XC5VLX110T-1FF1738C
• Description: IC FPGA VIRTEX-5 110K 1738FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-1FF1738C

• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 5455872
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1738-500-G - BOARD DEV VIRTEX 5 FF1738
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
306
Nominal PCB Specifications
PCB Construction
Signal Return Current Management
Load Traces
Power Distribution System Design
The nominal SSO table
parameters meet the following requirements.
Note:
SSO Calculator must be used to determine the SSO limit, according to the physical factors of the
unique PCB.
•
•
•
•
•
•
•
•
•
V
Total board thickness must be no greater than 62 mils (1575 µ).
Traces must be referenced to a plane on an adjacent PCB layer.
The reference plane must be either GND or the V
driver.
The reference layer must remain uninterrupted for its full length from device to
device.
All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ± 10%.
Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Designed according to the Virtex-5 FPGA PCB Designer’s Guide.
•
•
V
CCO
CCO
In cases where PCB parameters do not meet all requirements listed below, the Virtex-5 FPGA
Decoupling capacitors per the device guideline
Approved solder land patterns
and GND vias should have a drill diameter no less than 11 mils (279 µ).
and GND planes cannot be separated by more than 5.0 mils (152 µ)
(Table
www.xilinx.com
6-40) contains SSO limits for cases where the PCB
CCO
associated with the output
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010