XCV2000E-7FG680C Xilinx Inc, XCV2000E-7FG680C Datasheet - Page 47

• Manufacturer Part Number: XCV2000E-7FG680C
• Description: IC FPGA 1.8V C-TEMP 680-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV2000E-7FG680C

• Number Of Logic Elements/cells: 43200
• Number Of Labs/clbs: 9600
• Total Ram Bits: 655360
• Number Of I /o: 512
• Number Of Gates: 2541952
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 680-LBGA Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Examples
Creating a design with the SelectI/O features requires the
instantiation of the desired library symbol within the design
code. At the board level, designers need to know the termi-
nation techniques required for each I/O standard.
This section describes some common application examples
illustrating the termination techniques recommended by
each of the standards supported by the SelectI/O features.
Termination Examples
Circuit examples involving typical termination techniques for
each of the SelectI/O standards follow. For a full range of
accepted values for the DC voltage specifications for each
standard, refer to the table associated with each figure.
The resistors used in each termination technique example
and the transmission lines depicted represent board level
components and are not meant to represent components
on the device.
GTL
A sample circuit illustrating a valid termination technique for
GTL is shown in
Table 23
Table 23: GTL Voltage Specifications
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Notes:
1.
V
V
V
V
V
V
V
I
I
I
OH
OL
OL
OH
OL
CCO
REF
TT
IH
IL
at V
at V
N must be greater than or equal to 0.653 and less than or
equal to 0.68.
= V
= V
at V
= N × V
REF
OL
OL
REF
Parameter
OH
V
lists DC voltage specifications.
(mA) at 0.4V
(mA) at 0.2V
GTL
CCO
(mA)
R
– 0.05
+ 0.05
TT
Figure 44: Terminated GTL
= N/A
1
Figure
50Ω
V
TT
44.
= 1.2V
V
REF
0.74
1.14
0.79
Min
32
-
-
-
-
-
-
= 0.8V
Z = 50
50Ω
V
TT
= 1.2V
0.85
0.75
Typ
N/A
0.8
1.2
0.2
x133_08_111699
-
-
-
-
Max
0.86
1.26
0.81
0.4
40
www.xilinx.com
-
-
-
-
-
GTL+
A sample circuit illustrating a valid termination technique for
GTL+ appears in
appear in
Table 24: GTL+ Voltage Specifications
Notes:
1.
V
V
V
V
V
V
V
I
I
I
OH
OL
OL
OH
OL
CCO
REF
TT
IH
IL
at V
at V
N must be greater than or equal to 0.653 and less than or
equal to 0.68.
= V
= V
at V
Virtex™-E 1.8 V Field Programmable Gate Arrays
= N × V
Parameter
REF
OL
OL
REF
OH
Table
(mA) at 0.6V
(mA) at 0.3V
V
– 0.1
(mA)
CCO
+ 0.1
Figure 45: Terminated GTL+
TT
24.
1
= N/A
50Ω
V
Figure
TT
V
= 1.5V
REF
45. DC voltage specifications
GTL+
Z = 50
0.88
1.35
0.98
Min
= 1.0V
0.3
36
-
-
-
-
-
50Ω
V
TT
= 1.5V
x133_09_012400
0.45
Typ
1.0
1.5
1.1
0.9
-
-
-
-
-
Module 2 of 4
Max
1.12
1.65
1.02
0.6
48
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-
-
-
-
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