XC4010XL-09BG256C Xilinx Inc, XC4010XL-09BG256C Datasheet - Page 13

• Manufacturer Part Number: XC4010XL-09BG256C
• Description: IC FPGA C-TEMP 3.3V 256-PBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4010XL-09BG256C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature)
DS005 (v. 1.8 October 18, 1999 - Product Specification
Clocks
Clock Enable (EC) to Clock (IK)
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
Setup Times
Pad to Clock (IK), no delay
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
Pad to Fast Capture Latch Enable (OK), no
delay
Hold Times
All Hold Times
Global Set/Reset
Minimum GSR Pulse Width
Global Set/Reset
Delay from GSR input to any Q
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch,
no delay
Pad to I1, I2 via transparent FCL and in-
put latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
(via transparent standard input latch)
R
Description
XC4000E and XC4000X Series Field Programmable Gate Arrays
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
PICKF
POCK
MRW
OKLI
ECIK
OKIK
PICK
PFLI
RRI*
IKRI
IKLI
PID
PLI
XC4013, 36, 62XL
XC4013, 36, 62XL
XC4013, 36, 62XL
Balance of Family
Balance of Family
Balance of Family
XC4013, 36, 62XL
XC4013, 36, 62XL
XC4013, 36, 62XL
XC4013, 36, 62XL
Balance of Family
Balance of Family
Balance of Family
Balance of Family
All devices
XC4002XL
All devices
All devices
XC4002XL
All Devices
All devices
XC4002XL
XC4002XL
XC4002XL
All devices
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
X4002XL
Device
Speed Grade
.
19.8
Max
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
Min
1.6
4.7
3.1
3.1
5.4
3.7
3.7
1.7
1.8
5.2
3.6
3.6
0.1
3.0
2.2
2.2
2.6
1.7
1.7
3.2
2.3
2.3
1.2
1.2
9.8
-3
0
17.3
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
Max
Min
1.4
4.2
2.7
2.7
4.7
3.3
3.3
1.5
1.6
4.6
3.1
3.1
0.1
2.7
1.9
1.9
2.3
1.5
1.5
2.9
2.0
2.0
1.0
1.0
8.5
9.8
-2
0
15.0
Max
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
Min
1.2
3.6
2.4
2.4
4.1
2.8
2.8
1.3
1.4
4.0
2.7
2.7
0.1
2.3
1.6
1.6
2.0
1.3
1.3
2.5
1.8
1.8
0.9
0.9
7.4
8.5
-1
0
14.0
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
Max
All devices are 100%
Min
1.1
3.5
2.2
2.2
3.9
2.7
2.7
1.2
1.3
3.8
2.6
2.6
-09
0.1
2.3
1.6
1.6
2.0
1.3
1.3
2.4
1.7
1.7
0.9
0.9
7.0
8.1
0
14.0
Max
10.9
16.2
20.4
Min
1.0
2.1
2.5
1.2
1.3
2.5
-08
0.1
1.6
1.2
1.6
0.9
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-85
6