XC4062XL-09BG560C Xilinx Inc, XC4062XL-09BG560C Datasheet - Page 5

• Manufacturer Part Number: XC4062XL-09BG560C
• Description: IC FPGA C-TEMP 3.3V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4062XL-09BG560C

• Number Of Logic Elements/cells: 5472
• Number Of Labs/clbs: 2304
• Total Ram Bits: 73728
• Number Of I /o: 384
• Number Of Gates: 62000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000XL CLB Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
CLB Switching Characteristic Guidelines
DS005 (v. 1.8 October 18, 1999 - Product Specification
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
Add/Subtract input (F3) to C
Initialization inputs (F1, F3) to C
C
C
Carry Net Delay, C
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz) (for export control)
IN
IN
through function generators to X/Y outputs
to C
OUT
, bypass function generators
R
OUT
Description
to C
IN
OUT
OUT
OUT
XC4000E and XC4000X Series Field Programmable Gate Arrays
Speed Grade
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
ILO
IHO
ITO
HH0O
HH1O
HH2O
CBYP
OPCY
ASCY
INCY
SUM
BYP
NET
CKO
CKLO
ICK
IHCK
HH0CK
HH1CK
HH2CK
DICK
ECCK
RCK
CCK
CHCK
CKI
CKIH
CKHH0
CKHH1
CKHH2
CKDI
CKEC
CKR
CH
CL
RPW
RIO
MRW
MRQ
TOG
Symbol
(MHz)
Min
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
3.0
3.0
3.0
0
0
0
0
0
0
0
0
See
-3
Table on page 85
Max
0.26
0.32
19.8
166
1.6
2.7
2.9
2.5
2.4
2.5
1.5
2.7
3.3
2.0
2.8
2.1
2.1
3.7
Min
1.0
1.9
1.7
1.6
1.7
0.8
0.9
0.5
2.1
3.0
2.8
2.8
2.8
0
0
0
0
0
0
0
0
-2
Max
0.23
0.28
17.3
179
1.5
2.4
2.6
2.2
2.1
2.2
1.3
2.3
2.9
1.8
2.6
1.9
1.9
3.2
for T
Min
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
2.5
2.5
2.5
0
0
0
0
0
0
0
0
RRI
-1
values per device.
Max
0.20
0.25
15.0
200
1.3
2.2
2.2
2.0
1.9
2.0
1.1
2.0
2.5
1.5
2.4
1.6
1.6
2.8
Min
0.8
1.6
1.4
1.2
1.4
0.6
0.7
0.4
1.3
2.1
2.3
2.3
2.3
0
0
0
0
0
0
0
0
All devices are 100%
-09
Max
0.14
0.24
14.0
217
1.2
2.0
2.0
1.8
1.6
1.8
1.0
1.6
1.8
1.0
1.7
1.5
1.5
2.7
Min
0.8
1.5
1.4
1.1
1.4
0.6
0.7
0.4
1.2
2.0
2.1
2.1
2.3
0
0
0
0
0
0
0
0
-08
Max
0.14
0.24
14.0
238
1.1
1.9
1.8
1.8
1.5
1.8
0.9
1.6
1.8
0.9
1.5
1.4
1.4
2.6
6-77
6