ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet
ATAM862P-TNSY4D
Specifications of ATAM862P-TNSY4D
Related parts for ATAM862P-TNSY4D
ATAM862P-TNSY4D Summary of contents
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Features • Single Package Fully-integrated 4-bit Flash Microcontroller with RF Transmitter • Low Power Consumption in Sleep Mode (< 1 µA Typically) • Maximum Output Power with Low Supply Current • 2.0V to 4.0V Operation Voltage for Single Li-cell Power ...
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Pin Configuration Figure 2-1. Pinning SSO24 Table 2-1. Pin Description: RF Part Pin Symbol Function 1 XTAL Connection for crystal 2 VS Supply voltage 3 GND Ground 4 ENABLE Enable input ATAM862-4 2 XTAL 1 24 ANT1 VS 2 ...
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Table 2-1. Pin Description: RF Part (Continued) Pin Symbol Function Clock output signal for microcontroller, 21 CLK the clock output frequency is set by the crystal to f Switches on power amplifier, used for 22 PA_ENABLE ASK modulation 23 ANT2 ...
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UHF ASK/FSK Transmitter Block 4. Features • Integrated PLL Loop Filter • ESD Protection (4 kV HBM/200 V MM, Except Pin HBM/100 V MM) also at ANT1/ANT2 • Maximum Output Power (10 dBm) with Low Supply ...
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Figure 5-1. Block Diagram CLK PA_ENABLE ANT2 ANT1 OSC2 OSC1 NRESET BP10 BP13 BP20/NTE BP21 BP22 BP23 4551G–4BMCU–07/07 ATAM862 Power up / down PFD VCO PLL Brown-out protect. RC ...
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General Description The fully-integrated PLL transmitter that allows particularly simple, low-cost RF miniature trans- mitters to be assembled. The VCO is locked to 32 × f for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are ...
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Figure 7-1. Using C tances on each side of the crystal of C crystal of C typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz results. 7.3 CLK Output An output CLK signal is provided for a connected ...
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Figure 7-2. 7.4 Application Circuit For the supply-voltage blocking capacitor C 7-3 on page 9 power amplifier where C for C two capacitors in series should be used to achieve a better tolerance value and to have 2 the possibility ...
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Figure 7-3. ASK Application Circuit C4 XTAL 1 XTAL GND 3 ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 4551G–4BMCU–07/07 XTO VCO ...
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Figure 7-4. FSK Application Circuit C4 XTAL 1 C5 XTAL GND 3 ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 ATAM862-4 10 XTO VCO PA ...
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Figure 7-5. ESD Protection Circuit VS GND 8. Absolute Maximum Ratings: RF Part Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device ...
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Electrical Characteristics (Continued 2.0V to 4.0V –40°C to +125°C unless otherwise specified. S amb Typical values are given 3.0V and T S Parameters Test Conditions T Output power variation for the full ...
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... EEPROM block during programming. The configuration is downloaded to the I/Os with every power-on reset. 14. Introduction The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrollers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multi- function timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators ...
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Differences between ATAM862-4 and ATAR862 Microcontrollers 14.1.1 Program Memory The program memory of the devices is realized as an EEPROM. The memory size for user pro- grams is 4096 bytes programmed as 258 × 16 bytes blocks ...
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MARC4 Architecture General Description The microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip peripher- als. The CPU is based on the Harvard architecture with physically separated program memory (ROM) and data memory (RAM). Three independent buses, ...
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Program Memory The program memory (EEPROM) is programmable with the customer application program dur- ing the fabrication of the microcontroller. The EEPROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4-Kbytes. ...
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Figure 16-2. RAM Map 16.3 Registers The microcontroller has seven programmable registers and one condition code register (see Figure 16.3.1 Program Counter (PC) The program counter is a 12-bit register which contains the address of the next instruction to be ...
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RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. 16.3.3 Expression Stack Pointer (SP) The stack pointer ...
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Interrupt Enable (I) The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or while executing the DI instruction, the interrupt enable flag is reset, ...
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Interrupt Structure The microcontroller can handle interrupts with eight different priority levels. They can be gener- ated from the internal and external interrupt sources software interrupt from the CPU itself. Each interrupt level has a hard-wired ...
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Figure 16-5. Interrupt Handling INT3 4 3 INT3 active Main / Autosleep Table 16-1. Interrupt Priority Interrupt Priority INT0 Lowest INT1 | INT2 | INT3 | INT4 | INT5 | INT6 | INT7 Highest ...
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Table 16-2. Hardware Interrupts Interrupt Register INT1 INT2 INT3 INT4 T3CM1 INT5 T3CM2 INT6 INT7 16.8 Software Interrupts The programmer can generate interrupts by using the software interrupt instruction (SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. ...
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Master Reset The master reset forces the CPU into a well-defined condition unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power ...
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A power-on reset pulse is generated brown-out reset pulse is generated when V values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. When the controller runs in the upper supply ...
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Figure 18-1. Voltage Monitor 18.0.1 Voltage Monitor Control/Status Register VMC: Write VMST: Read VM2: VM1: VM0: Table 18-1. VM2 VIM VMS 4551G–4BMCU–07/07 Voltage monitor BP41/ IN VMI VMC : VM2 VM1 VM0 ...
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Figure 18-2. Internal Supply Voltage Supervisor Figure 18-3. External Input Voltage Supervisor 19. Clock Generation 19.1 Clock Module The ATAM862-4 contains a clock module with 4 different internal oscillator types: two RC-oscil- lators, one 4-MHz crystal oscillator and one 32-kHz ...
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In this state an interrupt can wake up the controller with the RC-oscillator, and the external oscil- lator can be activated and selected by software. A synchronization stage avoids too short clock periods if the clock source or the clock ...
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The basic center frequency of the RC-oscillator default after power-on reset. Figure 19-2. RC-oscillator 1 19.2.2 External Input Clock The OSC1 or OSC2 ...
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RC-oscillator 2 with External Trimming Resistor The RC-oscillator high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and V lator 2 frequency can be maintained stable with a ...
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Oscillator Some applications require long-term time keeping or low resolution timing. In this case, an on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the SYSCL. In this mode, power consumption is ...
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Table 19-3. 19.3.2 System Configuration Register (SC) SC: write BOT OS1 OS0 Table 19-4. Mode Note: 20. Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system power consumption ...
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The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. For standard applications use the $AUTOSLEEP routine ...
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Figure 21-1. Example of I/O Addressing Module ASW (Address Pointer) Subaddress Reg. Auxiliary Switch Module Primary Reg. Indirect Subport Access (Subport Register Write) 1 Addr. (SPort) Addr. (M1) OUT 2 SPort _Data (Subport Register Read) 1 Addr. (SPort) Addr. (M1) ...
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Table 21-1. Peripheral Addresses Port Address Name 1 P1DAT 2 P2DAT Auxiliary P2CR 3 SC CWD Auxiliary CM 4 P4DAT Auxiliary P4CR 5 P5DAT Auxiliary P5CR 6 P6DAT Auxiliary P6CR 7 T12SUB Subport address 0 T2C 1 T2M1 2 T2M2 ...
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Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). ...
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Figure 22-1. Bi-directional Port 1 22.2 Bi-directional Port 2 As all other bi-directional ports, this port includes a bitwise programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up ...
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Figure 22-2. Bi-directional Port 2 22.2.1 Port 2 Data Register (P2DAT) Bit 3 * P2DAT3 * Bit 3 -> MSB, Bit 0 -> LSB 22.2.2 Port 2 Control Register (P2CR) Bit 3 P2CR3 Value: 1111b means all pins in input ...
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Bi-directional Port 5 As all other bi-directional ports, this port includes a bitwise programmable Control Register (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the ...
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Port 5 Data Register (P5DAT) Bit 3 P5DAT3 22.3.2 Port 5 Control Register (P5CR) Byte Write First write cycle Second write cycle P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code Table 22-2. Port 5 Control Register Auxiliary Address: "5"hex, ...
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Bi-directional Port 4 The bi-directional Port bitwise configurable I/O port and provides the external pins for the Timer 2, SSI and the voltage monitor input (VMI normal port, it performs in exactly the same ...
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Table 22-3. Auxiliary Address: "4"hex Code ...
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Table 22-4. Auxiliary Address: "6"hex Code 22.6 Universal Timer/Counter/ Communication Module (UTCM) The Universal Timer/counter/Communication Module (UTCM) consists of three timers (Timer 1,Timer 2, ...
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Figure 22-6. UTCM Block Diagram T3I T2I 22.7 Timer 1 The Timer interval timer which can be used to generate periodical interrupts and as pres- caler for Timer 2, Timer 3, the serial interface and the watchdog ...
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This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1. Timer 1 can also be used as a watchdog ...
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Timer 1 Control Register 1 (T1C1) Bit 3 * T1RM * Bit 3 -> MSB, Bit 0 -> LSB T1RM T1C2 T1C1 T1C0 The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval depends on ...
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Timer 1 Control Register 2 (T1C2) Bit 3 * – * Bit 3 -> MSB, Bit 0 -> LSB T1BP T1CS T1IM 22.7.3 Watchdog Control Register (WDC) Bit 3 * WDL * Bit 3 -> MSB, Bit 0 -> ...
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Timer 2 8-/12-bit Timer for: • Interrupt, square-wave, pulse and duty cycle generation • Baud-rate generation for the internal shift register • Manchester and Biphase modulation together with the SSI • Carrier frequency generation and modulation together with the ...
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Figure 22-9. Timer 2 T2I SYSCL CL2/1 T1OUT 4-bit Counter 2/1 TOG3 SCL RES T2C Compare 2/1 T2CO1 22.9 Timer 2 Modes 22.9.1 Mode 1: 12-bit Compare Counter The 4-bit stage and the 8-bit stage work together as a 12-bit ...
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Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler Figure 22-11. 8-bit Compare Counter CL2/1 4-bit counter RES 4-bit compare CM1 4-bit register The 4-bit stage is used as programmable prescaler for the 8-bit counter stage. In this mode, ...
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Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can ...
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Toggle Mode B: Figure 22-15. Pulse Generator – the Timer Output Toggles with the Timer Start if the T2TS bit Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-16. Pulse Generator – ...
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Timer 2 Output Mode 2 Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2) Figure 22-17. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output ...
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Timer 2 Output Mode 5 Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code Figure 22-20. Manchester Modulation 22.11.6 Timer 2 Output Mode 7 In this mode the timer overflow defines the period and ...
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Timer 2 Control Register (T2C) Bit 3 T2CS1 T2CS1 T2CS0 Table 22-7. T2CS1 T2TS T2R 22.12.2 Timer 2 Mode Register 1 (T2M1) Bit 3 T2D1 T2D1 T2D0 Table 22-8. T2D1 T2MS1 ...
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Table 22-9. Mode 22.12.3 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 ...
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Table 22-10. Timer 2 Output Select Bits Output Mode If one of these output modes is used the T2O alternate function of Port 4 must also be activated. 22.12.5 Timer 2 Compare and Compare Mode Registers Timer 2 has two ...
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Timer 2 Compare Mode Register (T2CM) Bit 3 T2OTM T2OTM T2CTM T2RM T2IM Table 22-11. Timer 2 Toggle Mask Bits Timer 2 Output Mode and and 6 7 ...
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Timer 3 23.1 Features • Two Compare Registers • Capture Register • Edge Sensitive Input with Zero Cross Detection Capability • Trigger and Single Action Modes • Output Control Modes • Automatically Modulation and Demodulation Modes • FSK Modulation ...
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A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed ...
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Figure 23-2. Counter 3 Stage Capture register CL3 8-bit counter 8-bit comparator Compare register 1 Compare register 2 The status of the timer as well as the occurrence of a compare match or an edge detect of the input signal ...
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Figure 23-4. Counter Reset with Compare Register 2 and Toggle with Start Figure 23-5. Single Action of Compare Register 1 Counter 3 23.2.2 Timer 3 – Mode 2: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) The counter ...
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Timer 3 – Mode 3: Timer/Counter, Internal Trigger Restart and Internal Capture (with TOG2) The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the counter. The counter value ...
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Timer 3 Modulator/Demodulator Modes 23.3.1 Timer 3 – Mode 6: Carrier Frequency Burst Modulation Controlled by Timer 2 Output Toggle Flip-Flop (M2) The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare ...
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Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output pulse ...
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Timer 3 – Mode 11: Biphase Demodulation In the Biphase demodulation mode, the timer operates like in Manchester demodulation mode. The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in the ...
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Timer 3 Modulator for Carrier Frequency Burst Modulation If the output stage operates as pulse-width modulator for the shift register, the output can be stopped with stage 1 of Timer 2. For this task, the timer mode 3 must ...
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Timer 3 Registers 23.6.1 Timer 3 Mode Register (T3M) Bit 3 T3M3 T3M3 T3M2 T3M1 T3M0 Table 23-1. Mode Note: 4551G–4BMCU–07/07 Bit 2 ...
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Timer 3 Control Register 1 (T3C) Write Write T3EIM T3TOP T3TS T3R 23.6.3 Timer 3 Status Register 1 (T3ST) Read Read T3ED T3C2 T3C1 Note: ATAM862-4 68 Bit 3 Bit 2 Bit 1 T3EIM T3TOP T3TS Timer 3 Edge ...
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Timer 3 Clock Select Register (T3CS) T3CS T3E1 T3E0 Table 23-2. T3E1 T3CS1 Timer 3 Clock Source select bit 1 T3CS0 Timer 3 Clock Source select bit 0 Table 23-3. T3CS1 23.6.5 Timer 3 Compare- and Compare-mode Register Timer ...
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Timer 3 Compare-Mode Register 1 (T3CM1) T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1 23.6.7 Timer 3 Compare Mode Register 2 (T3CM2) T3CM2 T3SM2 T3TM2 T3RM2 ...
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The compare registers and corresponding counter reset masks can be used to program the counter time intervals and the toggle masks can be used to program output signal. The sin- gle-action mask can also be used in this mode. It ...
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Synchronous Serial Interface (SSI) 23.8.1 SSI Features: • With Timer 1 – 2- and 3-wire NRZ – 2-wire mode multi-chip link mode (MCL), additional internal 2-wire link for multi-chip • With Timer 2 – Biphase modulation – Manchester modulation ...
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Multi-chip link (MCL) – the SSI can also be used as an interchip data interface for use in single package multi-chip modules or hybrids. For such applications, the SSI is pro- vided with two dedicated pads (MCL_SD and MCL_SC) ...
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At the beginning of every telegram, the SSI control loads the transmit buffer into the shift register and proceeds immediately to shift data serially out. At the same time, incoming data is shifted into the shift register input. This incoming ...
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SSI will continue clocking in the next telegram. Should, however, the first telegram not have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in the shift register until a certain point ...
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Shift Mode (MCL) In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e always generated and output by the SSI. Both ...
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Figure 23-20. Example of MCL Receive Dialog SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) 23.8.6 8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl- edge bit which ...
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Figure 23-21. MCL Bus Protocol Bus not busy (1) Start data transfer (2) Stop data transfer (3) Data valid (4) Acknowledge Figure 23-22. MCL Bus Protocol 23.8.8 SSI Interrupt The SSI interrupt INT3 can ...
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Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation pur- poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be ...
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Serial Interface Registers 23.9.1 Serial Interface Control Register 1 (SIC1) Bit 3 SIR SIR SCD Note: SCS1 SCS0 Note: Table 23-4. • In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY ...
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Serial Interface Control Register 2 (SIC2) Bit 3 MSM MSM SM1 SM0 Table 23-5. Mode SDD Note: 4551G–4BMCU–07/07 Bit 2 Bit 1 Bit 0 SM1 SM0 SDD Modular Stop Mode MSM = 1, modulator stop ...
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Serial Interface Status and Control Register (SISC) Write Read MCL RACK TACK SIM IFN SRDY ACT 23.9.4 Serial Transmit Buffer (STB) – Byte Write First write cycle Second write cycle T he STB is the transmit buffer of the ...
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Serial Receive Buffer (SRB) – Byte Read First read cycle Second read cycle T he SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads content into the ...
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Combination Mode 1: Burst Modulation SSI mode 1: Timer 2 mode Timer 2 output mode 3: Figure 24-2. Carrier Frequency Burst Modulation with the SSI Internal Data Output Counter 2 24.1.2 Combination Mode 2: ...
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Combination Mode 3: Manchester Modulation 1 SSI mode 1: Timer 2 mode Timer 2 output mode 5: Figure 24-4. Manchester Modulation 1 24.1.4 Combination Mode 4: Manchester Modulation 2 SSI mode 1: Timer 2 ...
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Combination Mode 5: Biphase Modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 4: The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI ...
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Combination Mode Timer 3 and SSI Figure 24-7. Combination Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 TOG2 POUT T1OUT SYSCL 4551G–4BMCU–07/07 I/O-bus CP3 T3CP 8-bit counter 3 T3C Compare 3/2 Timer ...
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Combination Mode 6: FSK Modulation SSI mode 1: Timer 3 mode 8: The two compare registers are used to generate two varied time intervals. The SSI data output selects which compare register is used for the output frequency generation. ...
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Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation SSI mode 1: Timer 3 mode 10: For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The ...
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Combination Mode 9: Biphase Demodulation SSI mode 1: Timer 3 mode 11: In the Biphase demodulation mode the timer works like in the Manchester demodulation mode. The difference is that the bits are decoded with the toggle flip-flop. This ...
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Combination Mode Timer 2 and Timer 3 Figure 24-12. Combination Timer 3 and Timer 2 T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit counter 2/1 T1OUT SCL RES Compare 2/1 T2C ...
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Figure 24-13. Frequency Measurement Counter 3 Figure 24-14. Event Counter with Time Gate Counter 3 Register 24.3.2 Combination Mode 11: Burst Modulation 1 Timer 2 mode 1/2: Timer 2 output mode 1/6: Timer 3 mode 6: The Timer 3 counter ...
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Combination Mode Timer 2, Timer 3 and SSI Figure 24-16. Combination Timer 2, Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL 8-bit Counter 3 T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit Counter 2/1 T1OUT ...
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Combination Mode 12: Burst Modulation 2 SSI mode 1: Timer 2 output mode 2: Timer 2 output mode 1/6: Timer 3 mode 7: The Timer 3 counter is driven by an internal or external clock source. Its compare- and ...
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Figure 24-18. FSK Modulation Counter 3 24.5 Data EEPROM The internal data EEPROM offers 2 pages of 512 bits each. Both pages are organized as 32 × 16-bit words. The programming voltage as well as the write cycle timing is ...
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Serial Interface The EEPROM uses a two-wire serial interface (TWI) to the microcontroller for read and write accesses to the data considered slave in all these applications. That means, the controller has to be ...
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Control Byte Format Start Start 24.7 EEPROM The EEPROM has a size of 2 × 512 bits and is organized as 32 × 16-bit matrix each. To read and write data to and from the EEPROM the serial interface ...
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Write One Data Byte Start 24.7.5 Write Two Data Bytes Start 24.7.6 Write Control Byte Only Start 24.7.7 Write Control Bytes Write low byte first Byte order Write high byte first Byte order A -> acknowledge; HB: high byte; ...
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Read One Data Byte Start 24.7.10 Read Two Data Bytes Start 24.7.11 Read n Data Bytes Start 24.7.12 Read Control Bytes Read low byte first, address increment Byte order Read high byte first, address decrement Byte order A -> ...
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Absolute Maximum Ratings: Microcontroller Block Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond ...
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DC Operating Characteristics (Continued 0V –40°C to +125°C unless otherwise specified. SS amb Parameters Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis Voltage Monitor Threshold Voltage VM high threshold voltage VM ...
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AC Characteristics Supply voltage V = 1.8 to 4.0V Parameters Operation Cycle Time System clock cycle Timer 2 input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH time ...
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AC Characteristics (Continued) Supply voltage V = 1.8 to 4.0V Parameters 32-kHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) External 32-kHz Crystal Parameters Crystal frequency Serial resistance Static capacitance Dynamic ...
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Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a ...
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Ordering Information (1) Extended Type Number ATAM862x-TNQYzf ATAM862x-TNSYzf Note Hardware revision z = Operating temperature range J (–40°C to +125°C) + lead free frequency range = 4 (433 MHz) 32. Package Information 0.25 ...
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Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4551G-4BMCU-07/07 4551F-4BMCU-05/06 4551E-4BMCU-09/04 ATAM862-4 106 History • Put datasheet in a new template ...
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Table of Contents 1 Description .............................................................................................1 2 Pin Configuration ...................................................................................2 3 UHF ASK/FSK Transmitter Block .........................................................4 4 Features ..................................................................................................4 5 Description .............................................................................................4 6 General Description ...............................................................................6 7 Functional Description ..........................................................................6 8 Absolute Maximum Ratings: RF Part .................................................11 9 Thermal ...
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Master Reset .........................................................................................23 18 Voltage Monitor ....................................................................................24 19 Clock Generation .................................................................................26 20 Power-down Modes .............................................................................31 21 Peripheral Modules ..............................................................................32 22 Bi-directional Ports ..............................................................................35 23 Timer 3 ..................................................................................................58 ATAM862-4 108 16.9 Hardware Interrupts ......................................................................................22 17.1 Power-on Reset and Brown-out Detection ...
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Combination Modes .............................................................................83 25 Absolute Maximum Ratings: Microcontroller Block .......................100 26 Thermal Resistance ...........................................................................100 27 DC Operating Characteristics ...........................................................100 28 AC Characteristics .............................................................................102 29 Crystal Characteristics ......................................................................103 30 Emulation ............................................................................................104 31 Ordering Information .........................................................................105 32 Package Information ..........................................................................105 33 ...
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