CY7C64613-52NC Cypress Semiconductor Corp, CY7C64613-52NC Datasheet - Page 8

• Manufacturer Part Number: CY7C64613-52NC
• Description: IC MCU USB EZ FX 8K RAM 52-PQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX™r

Specifications of CY7C64613-52NC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C646xx
• Ram Size: 8K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 16
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1311

either synchronously (using strobe signals and a clock) or asynchronously (using strobe signals only). The slave FIFO data is
available as two 8-bit buses, which may be used simultaneously to operate as a single 16-bit data bus. The 16-bit connection,
along with fast double-byte mode, combine to give fast conversion between 8 and 16 bit buses. A flexible set of FIFO flags (full,
empty, and programmable) provide FIFO flow control.
2.7
With many sources and destinations for USB data, such as endpoint buffers, slave FIFOs, and internal/external RAM buffers, it
is important to move blocks of data between them quickly. Using internal DMA, the 8051 sets up source, destination, and transfer
length registers, and then initiates a DMA transfer. The maximum DMA transfer rate occurs between internal resources, such as
endpoint buffers and slave FIFOs. This maximum rate is one byte per 48-MHz clock, or 48 Mbytes per second.
2.8
The GPIF is a flexible 8 or 16-bit parallel interface driven by a user-programmable set of vectors that operate similarly to a finite
state machine. It allows the CY7C646xx to perform local bus mastering, and can implement a wide variety of protocols such as
ATAPI, printer parallel port, and Utopia.
The GPIF has six programmable Control Outputs (CTL), six Address Outputs (ADR), and six general purpose Ready Inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, or determines what
state a ready input (or multiple inputs) must be before proceeding. A sequence of the GPIF vectors make up a single waveform
that will be executed to perform the desired data move between the CY7C646xx and the external design.
Document #: 38-08005 Rev. **
DMA
GPIF (General Programmable Interface)
CY7C64601/603/613
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