CY7C63723-PXC Cypress Semiconductor Corp, CY7C63723-PXC Datasheet - Page 31

• Manufacturer Part Number: CY7C63723-PXC
• Description: IC MCU 8K USB/PS2 LS 18DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™r

Specifications of CY7C63723-PXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C637xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 10
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1620

Bit [7:0]: P0 [7:0] Interrupt Enable
Bit [7:0]: P1 [7:0] Interrupt Enable
Document #: 38-08022 Rev. *B
Read/Write
Read/Write
Figure 21-4. Port 0 Interrupt Enable Register (Address
Bit Name
Bit Name
1 = Enables GPIO interrupts from the corresponding input
pin.
0 = Disables GPIO interrupts from the corresponding input
pin.
1 = Enables GPIO interrupts from the corresponding input
pin.
Reset
Reset
Wake-up
Int
Bit #
Bit #
Figure 21-5. Port 1 Interrupt Enable Register
USB-
PS/2
Int
EP2
Int
1
1
1
W
W
7
0
7
0
D
D
CLK
CLK
D
CLK
CLR
CLR
CLR
W
W
6
0
6
0
(Address 0x05)
Q
Q
Q
(Reg 0x21)
Enable [2]
(Reg 0x20)
(Reg 0x20)
Enable [0]
Enable [7]
W
0x04)
W
P0 Interrupt Enable
P1 Interrupt Enable
5
0
5
0
W
W
4
0
4
0
Figure 21-3. Interrupt Controller Logic Block Diagram
FOR
FOR
W
W
3
0
3
0
W
W
2
0
2
0
W
W
1
0
1
0
SPI CLR
SPI IRQ
Capture A CLR
Capture A IRQ
Capture B CLR
Capture B IRQ
USB-PS/2 IRQ
128- µ s CLR
128- µ s IRQ
1-ms CLR
1-ms IRQ
EP0 IRQ
EP1 CLR
EP1 IRQ
EP2 CLR
EP2 IRQ
GPIO CLR
GPIO IRQ
Wake-up CLR
EP0 CLR
USB-PS/2 Clear
Wake-up IRQ
W
W
0
0
0
0
Interrupt
Encoder
Priority
The polarity that triggers an interrupt is controlled indepen-
dently for each GPIO pin by the GPIO Interrupt Polarity
Registers. Figure 21-6 and Figure 21-7 control the interrupt
polarity of each GPIO pin.
Bit [7:0]: P0[7:0] Interrupt Polarity
Read/Write
Read/Write
Bit Name
Bit Name
0 = Disables GPIO interrupts from the corresponding input
pin.
1 = Rising GPIO edge
0 = Falling GPIO edge
Reset
Reset
Bit #
Bit #
Interrupt
IRQout
Vector
Figure 21-6. Port 0 Interrupt Polarity Register
Figure 21-7. Port 1 Interrupt Polarity Register
W
W
7
0
7
0
Acknowledge
CPU
To CPU
Interrupt
Interrupt
Enable
W
W
Global
6
0
6
0
(Address 0x06)
(Address 0x07)
CLR
Bit
P0 Interrupt Polarity
W
P1 Interrupt Polarity
W
5
0
5
0
Controlled by DI, EI, and
RETI Instructions
W
W
4
0
4
0
IRQ Pending
W
W
(Bit 7, Reg 0xFF)
3
0
3
0
Sense
Int Enable
(Bit 2, Reg 0xFF)
CY7C63722
CY7C63723
CY7C63743
W
W
2
0
2
0
IRQ
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W
W
1
0
1
0
W
W
0
0
0
0