CY7C63001C-SXC Cypress Semiconductor Corp, CY7C63001C-SXC Datasheet - Page 9

• Manufacturer Part Number: CY7C63001C-SXC
• Description: IC MCU 4K USB MCU LS 20SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63001C-SXC

• Applications: USB Microcontroller
• Core Processor: M8A
• Program Memory Type: OTP (4 kB)
• Controller Series: CY7C630xx
• Ram Size: 128 x 8
• Interface: USB
• Number Of I /o: 12
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1850

Document #: 38-08026 Rev. *B
6.6
Interface with peripherals is conducted via as many as 16
GPIO signals. These signals are divided into two ports: Port 0
and Port 1. Port 0 contains eight lines (P0.0–P0.7) and Port 1
contains up to eight lines (P1.0–P1.7). The number of external
I/O pins depends on the package type. Both ports can be
accessed by the IORD, IOWR, and IOWX instructions. The
Port 0 data register is located at I/O address 0x00 while the
Port 1 data register is located at I/O address 0x01. The
contents of both registers are set HIGH during a reset. Refer
to Figures 6-7 and 6-8 for the formats of the data registers. In
addition to supporting general input/output functions, each I/O
line can trigger an interrupt to the microcontroller. Please refer
to the interrupt section for more details.
Each GPIO line includes an internal R
provides both the pull-up function and slew control. Two
factors govern the enabling and disabling of each resistor: the
state of its associated Port Pull-up register bit and the state of
the Data Register bit. NOTE: The control bits in the Port
Pull-up register are active LOW.
P0.7
P1.7
R/W
R/W
b7
b7
1
1
General Purpose I/O Ports
Port Pull-Up
Port Isink
P0.6
P1.6
R/W
R/W
Port Data
Register
Suspend
Register
Register
b6
b6
Data Bus
1
1
Bit
P0.5
P1.5
R/W
R/W
up
Figure 6-7. Port 0 Data Register (Address 0x00)
b5
Figure 6-8. Port 1 Data Register (Address 0x01)
b5
1
1
resistor. This resistor
Figure 6-9. Block Diagram of an I/O Line
P0.4
R/W
P1.4
R/W
b4
b4
1
1
Disable
Isink
DAC
A GPIO line is HIGH when a “1” is written to the Data Register
and a “0” is written to the respective Port Pull-up register.
Writing a “0” to the port Data Register disables the port’s
Pull-up resistor and outputs a LOW on the GPIO line
regardless of the setting in the Port Pull-up Register. The
output goes to a high-Z state if the Data Register bit and the
Port Pull-up Register bit are both “1”. Figure 6-9 illustrates the
block diagram of one I/O line. The Port Isink Register is used
to control the output current level and it is described later in
this section. NOTE: The Isink logic block is turned off during
suspend mode (please refer to the Instant-on Feature section
for more details). Therefore, to prevent higher I
during USB suspend mode, firmware must set ALL Port 0 and
Port 1 Data Register bits (which are not externally driven to a
known state), including those that are not bonded out on a
particular package, to “1” and all Port 0 and Port 1 Pull-Up
Register data bits to “0” to enable port pull-ups before setting
the Suspend bit (bit 3 of the Status and Control Register).
Table 6-2 is the Output Control truth table.
P0.3
P1.3
R/W
R/W
b3
b3
Schmitt
Trigger
1
1
V
CC
P0.2
P1.2
R/W
R/W
b2
b2
1
1
R
up
GPIO
Pin
P0.1
R/W
P1.1
R/W
b1
b1
1
1
CY7C63001C
CY7C63101C
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CC
P0.0
R/W
P1.0
R/W
b0
b0
1
currents
1