XS1-G04B-FB144-C4 XMOS, XS1-G04B-FB144-C4 Datasheet

IC MPU 32BIT QUAD CORE 144FBGA

XS1-G04B-FB144-C4

Manufacturer Part Number
XS1-G04B-FB144-C4
Description
IC MPU 32BIT QUAD CORE 144FBGA
Manufacturer
XMOS
Datasheet

Specifications of XS1-G04B-FB144-C4

Processor Type
XCore 32-Bit
Speed
1600MIPS
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
144-BGA
For Use With
XMOS AVB REF KIT - KIT REF AVB W/4 XS1-G-DK880-1016 - KIT REF LED RGB 16X32 W/XC-3880-1015 - BOARD KIT XS1-G4 LED CTRL TILE880-1014 - BOARD DEV KIT XS1-G4 ETHERNET880-1013 - BOARD DEV KIT XS1-G4880-1012 - KIT DEV 4CORE G4 W/LCD TOUCH
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
880-1008

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XS1-G04B-FB144-C4
Manufacturer:
XMOS
Quantity:
10 000
XS1-G4 144BGA Datasheet
Version 3.5
Publication Date: 2010/09/07
Copyright
© 2010 XMOS Ltd. All Rights Reserved.

Related parts for XS1-G04B-FB144-C4

XS1-G04B-FB144-C4 Summary of contents

Page 1

... XS1-G4 144BGA Datasheet Publication Date: 2010/09/07 Copyright © 2010 XMOS Ltd. All Rights Reserved. Version 3.5 ...

Page 2

... XS1-G4 144BGA Datasheet (3.5) Description The XS1-G family blends a powerful programmable fab- ric based on multi-threaded processors with a high-level programming language design flow. XMOS chips are general-purpose programmable devices that can be used in a wide range of applications and systems. The XS1-G4 device integrates four XCore™ devices. Each ...

Page 3

... XS1-G4 144BGA Datasheet (3.5) 1 Signal Descriptions This section describes the external signal pins of the XS1-G4 in the 144BGA package. The following I/O type conventions are used in this document 1.1 XCore Signals XCore signals can be used for generic I/O ports or for XMOS Links. All the XCore ...

Page 4

... XCore I/O configured as a 2wire link XLB[1:0]out 1.1.3 Precedence Ports and XMOS Links are connected to pins on the XS1-G4 by the program running on the device. The ports and links are multiplexed and follow a defined precedence if they overlap on the same core XMOS Link is enabled, the link has access to the pins; the pins of the underlying ports are disabled ...

Page 5

... XS1-G4 144BGA Datasheet (3.5) 1.2 Port Pin Table XCORES Package Ball Location Ball Name X0 X2 XnD0 J3 D10 XnD1 H3 E10 XnD2 G3 F10 XnD3 F3 G10 XnD4 E3 H10 XnD5 D3 J10 XnD6 C4 K9 XnD7 C5 K8 XnD8 C6 K7 XnD9 C7 K6 XnD10 C8 K5 XnD11 C9 K4 XnD12 K2 C11 ...

Page 6

... XS1-G4 144BGA Datasheet (3.5) 1.3 System Service Pin Table Signal SS_CLK SS_DEBUG SS_PLL_BYPASS SS_RESET SS_TCK SS_TDI 1.4 Core Power and Ground Pin Table Signal VDD VDD VDD VDD VDD VDD VDD VDD Ball ID Signal E4 SS_TDO E9 SS_TEST_ENA D4 SS_TMS D5 SS_TRST H9 SS_XC0_BS0 J8 Ball ID Signal ...

Page 7

... XS1-G4 144BGA Datasheet (3.5) 1.5 XCore I/O Power Table Signal IO VDD IO VDD IO VDD IO VDD IO VDD IO VDD IO VDD IO VDD 1.6 XMOS Link Pin Table See Section 1.2 Port Pin Table Ball ID Signal A1 IO VSS B6 IO VSS B11 IO VSS F2 IO VSS G11 IO VSS ...

Page 8

... IC power pins. Nominally 1.0V. SS_PLL_AGND Analogue ground for the PLL. Connect directly to board ground. SS_CLK Reference clock signal for the on-chip PLL. A default frequency of 20MHz is typically used by XS1 family devices but other frequencies can be derived from SS_CLK using an onboard PLL. Input clock frequencies of supported. ...

Page 9

... G4 latches the value driven onto this pin on the rising edge (de-assertion) of SS_RESET. The value driven should be static and configured using a pullup or pulldown resistor, as the XS1-G4 drives the boot status on this pin after reset. The value configured on this pin defines the boot mode for core 0 as follows: ...

Page 10

... XS1-G4 144BGA Datasheet (3.5) 2.3 JTAG Operation The XS1-G family supports a generic 5pin JTAG interface, which can be used to provide hardware testing including: Boundary scan testing for correct board connectivity Onboard source level debugging from remote terminals Boundary scanning for OTP ROM ...

Page 11

... XS1-G4 144BGA Datasheet (3.5) Register Number DEVICE_ID0 0x00 DEVICE_ID1 0x01 DEVICE_ID2 0x02 DEVICE_ID3 0x03 DBG_CTRL 0x04 DBG_INT 0x05 PLL_CLK_DIVIDER 0x06 SECURITY_CONFIG 0x07 PLINK[3:0] 0x10 : 0x13 DBG_SCRATCH[7:0] 0x20 : 0x27 T[7:0]_PC 0x40 : 0x47 T[7:0]_SR 0x60 : 0x67 The JTAG controller can read from the DBG_SCRATCH registers at the same time as the XCore, but if both devices write at the same time, the XCore write completes and the JTAG controller is ignored ...

Page 12

... XS1-G4 144BGA Datasheet (3. and Switching Characteristics 3.1 Operating Conditions Symbol Parameter IO_VDD I/O DC supply voltage VDD Core DC supply voltage SS_PLL_AVDD PLL analogue supply SS_PLL_DVDD PLL Digital DC Supply SS_OTP_VPP OTP external programming voltage Cl XCore I/O load capacitance Operating range (Commercial) Ta Operating range (Industrial) ...

Page 13

... XS1-G4 144BGA Datasheet (3.5) 2. Voltages with respect to IO VSS 3. Internal pull-up resistors are fitted to general purpose XCore I/O pins. Applies to both XCore I/O and XCore link I/Os. 4. Use for unused I/O only—the internal pull up resistor is not recommended as a substitute for an external pull-up resistor. ...

Page 14

... For further details on power consumption for XS1-G devices see the Consumption For XS1-G Devices Application that may result in high power consumption, please consider the thermally superior XS1-G4 512BGA package or make provision for forced air and/or heatsinks in your PCB layout. MIN TYP ...

Page 15

... Memory 3.7.1 Internal static memory The XS1-G4 has a total of 256K bytes of fast internal static memory for high rates of data throughput, divided into 64k bytes per XCore. Each internal memory access consumes one core clock cycle. There is no dedicated external memory interface, although memory can be expanded through appropriate use of the ports ...

Page 16

... ClkBlk The Input Valid window parameter relates to the capability of the XS1-G4 family devices to capture data input to the chip with respect to an external clock source. This parameter can be calculated as the sum of the input setup time and input hold time with regard to the external clock as measured at the G4 device pins. The output invalid window specifi ...

Page 17

... XS1-G4 144BGA Datasheet (3.5) absolute numbers since the G4 provides functionality to delay the incoming clock with respect to the incoming data. For further details on these parameters and on interfacing to higher speed synchronous interfaces see the relevant application note. 3.9 XMOS Link Interface Performance Symbol ...

Page 18

... XS1-G4 144BGA Datasheet (3.5) 4 Package Details 4.1 Package Pin Layout The following diagrams show the ball name and location for the BGA144 Package VDD X0D34 X0D35 B X0D33 IO VSS X0D18 C X0D32 X0D17 VDD D X0D31 X0D16 X0D5 E X0D30 X0D15 X0D4 F X0D29 IO VDD X0D3 ...

Page 19

... XS1-G4 144BGA Datasheet (3.5) 4.2 Package Mechanical Details www.xmos.com 19/22 ...

Page 20

... XS1-G4 144BGA Datasheet (3.5) 5 Device Configuration Example schematic diagrams detailing minimal system configurations may be found at: http://xmos.com/support/silicon 6 Device ID 6.1 XMOS JEDEC Manufacturer ID JEDEC is an international organization that manages standards in the electronic and semiconductor industries. XMOS has a unique Manufacturers ID which is: ...

Page 21

... Variant (000 standard product) Revision Mask (A-Z) Package Type Pin Count Temp Grade (C commercial 0-70C) Speed Grade (4 normal speed) 7.1 Orderable part numbers Part Number XS1-G04B-FB144-C4 XS1-G04B-FB144-I4 XS1 G 04 000 Package FBGA 144 0.8mm pitch FBGA 144 0.8mm pitch www.xmos.com 21/22 ...

Page 22

... Programming XC on XMOS Devices XS1-G System Specification XMOS Tools User Guide XS1 Assembly Language Manual XMOS XS1 32-Bit Application Binary Interface XS1-G Clock Frequency Control Application Note Estimating Power Consumption For XS1-G Devices Document History Date Release 2010-09-07 3.5 2010-06-07 3 ...

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