PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet
PCX755BVZFU300LE
Specifications of PCX755BVZFU300LE
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PCX755BVZFU300LE Summary of contents
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Features • 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755) • 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745) • 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745) • Selectable Bus Clock (12 CPU Bus Dividers up ...
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... Screening This product is manufactured in full compliance with: • HiTCE CBGA according to Atmel standards • CBGA + CI-CGA + FC-PBGA up screenings based upon Atmel standards • Full military temperature ranges (T • Industrial temperature ranges (T 1. General Description 1.1 Simplified Block Diagram The PC755 is targeted for low power systems and supports power management features such as doze, nap, sleep, and dynamic power management ...
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General Parameters The following list provides a summary of the general parameters of the PC755: Technology Die size Transistor count Logic design PC745 PC755 Core power supply I/O power supply 1.3 Features This section summarizes features of the PC755’s ...
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Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands – Fixed Point Unit 1 (FXU1)-multiply, divide, shift, rotate, arithmetic, logical – Fixed Point Unit 2 (FXU2)-shift, rotate, arithmetic, logical – Single-cycle arithmetic, shifts, rotates, logical – Multiply ...
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Copyback or write-through data cache (on a page basis, or for all L2) – Instruction-only mode and data-only mode. – 64 bytes (256K/512K) or 128 bytes (1M) sectored line size – Supports flow through (register-buffer) synchronous burst SRAMs, pipelined ...
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Pin Assignments Figure 2-1 viewed from the top surface. Part B shows the side profile of the PBGA package to indicate the direction of the top surface view. Figure 2-1. Figure 2-2 top surface. Part B shows the side ...
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Figure 2-2. 2138G–HIREL–05/06 Pinout of the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages as Viewed from the Top Surface Part ...
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Pinout Listings Table 2-1 Table 2-1. Pinout Listing for the PC745, 255 PBGA and HiTCE CBGA Packages Signal Name Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, - A[0 31] H1, E16, ...
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Table 2-1. Pinout Listing for the PC745, 255 PBGA and HiTCE CBGA Packages (Continued) Signal Name Pin Number MCP C13 - NC (No Connect) B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B5 C7, E5, ...
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Table 2-2 provides the pinout listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages Signal Name Pin Number A13, D2, H11, C1, B13, ...
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Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages Signal Name Pin Number L2AVDD L13 L2CE P17 L2CLKOUTA N15 L2CLKOUTB L16 U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, ...
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Table 2-2. Pinout Listing for the PC755, 360 PBGA, CBGA, HiTCE CBGA and CI-CGA Packages Signal Name Pin Number TEA J1 TLBISYNC A3 (6) TMS C8 (6) TRST A10 TSIZ[0 2] A9, B9 TT[0 4] ...
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Signal Description Figure 3-1. PC755 Microprocessor Signal Groups ADDRESS ARBITRATION ADDRESS START ADDRESS BUS TRANSFER ATTRIBUTE ADDRESS TERMINATION DATA ARBITRATION DATA TRANSFER DATA TERMINATION 2138G–HIREL–05/ ABB A[0-31] ...
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... Detailed Specifications This specification describes the specific requirements for the microprocessor PC755, in compli- ance with Atmel Grenoble standard screening. 5. Applicable Documents 1) MIL-STD-883: Test methods and procedures for electronics. 2) MIL-PRF-38535 appendix A: General specifications for microcircuits. The microcircuits are in accordance with the applicable documents and as specified herein. ...
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... Caution: The input threshold selection must agree with the OV 2. The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information, contact your local Atmel sales office. 2138G–HIREL–05/06 shows the allowable undershoot and overshoot voltage on the PC755 and PC745. ...
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Recommended Operating Conditions Characteristic (3) Core supply voltage (3) PLL supply voltage (3) L2 DLL supply voltage (2)(4)(5) Processor bus supply voltage (2)(4)(5) L2 bus supply voltage Input voltage Die-junction temperature Notes: 1. These are the recommended and tested ...
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Thermal Characteristics 6.1 Package Characteristics Table 6-1 Table 6-1. Package Thermal Characteristics Characteristic Junction-to-ambient thermal resistance, natural convection Junction-to-ambient thermal resistance, natural convection, four-layer ()(3) (2s2p) board Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer ()(3) (1s) board Junction-to-ambient thermal ...
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Table 6-3. Characteristic Junction to board thermal resistance The board designer can choose between several types of heat sinks to place on the PC755. There are several commercially-available heat sinks for the PC755 provided by the following vendors. For the ...
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Thermal Management Assistance The PC755 incorporates a thermal management assist unit (TAU) composed of a thermal sen- sor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). Specifications for the thermal sensor portion of the TAU are found ...
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Ultimately, the final selection of an appropriate heat sink depends on many factors, such as ther- mal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 6.1.4 Adhesives and Thermal Interface Materials Figure 6-3. A ...
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Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T Where : θ θ θ P During operation the die-junction temperatures (T specified in cooling the component greatly ...
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Assuming an air velocity of 0.5 m/s, we have an effective 30°C + 5°C+ (0.03°C/W +1.0°C/W + 7°C/W) × 5 resulting in a die-junction temperature of approximately 81°C which is well within the maximum operating ...
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When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping. • Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may ...
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Electrical Characteristics 8.1 Static Characteristics Table 8-1. DC Electrical Specifications at Recommended Operating Conditions (see (1) tions ” on page 16) Characteristic Input high voltage (all inputs except SYSLCK) Input low voltage (all inputs except SYSLCK) SYSCLK input high ...
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Clock AC Specifications Table 8-2 (1) ings ” on page Table 8-2. Clock AC Timing Specifications at Recommended Operating Conditions (See (1) Conditions ” on page Characteristic (1) Processor frequency (1) VCO frequency (1) SYSCLK frequency SYSCLK cycle time ...
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Table 8-3. Processor Bus Mode Selection AC Timing Specifications = 2.0V 100 mV; -55 ≤ 2.0V 100 mV DD Parameter (3)(4)(5)(6)(7) Mode select input setup to HRESET (3)(4)(6)(7)(8) HRESET to ...
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Table 8-4. Processor Bus AC Timing Specifications Parameter Setup Times: All Inputs Input Hold Times: TLBISYNC, MCP, SMI Input Hold Times: All Inputs, except TLBISYNC, MCP, SMI Valid Times: All Outputs Output Hold Times: All Outputs (2) SYSCLK to Output ...
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Figure 8-4 provides the input/output timing diagram for the PC755. Figure 8-4. Input/Output Timing Diagram SYSCLK All Inputs All Outputs (Except TS, ABB, ARTRY, DBB) TS, ABB, DBB AR TRY 8.2.1.2 L2 Clock AC Specifications The L2CLK frequency is programmed ...
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Functionality of core-to-L2 divisors 1.5 is verified at less than maximum rated frequencies. L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and ...
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The L2CLK_OUT timing diagram is shown in Figure 8-5. L2CLK_OUT Output Timing Diagram L2 Single-Ended Clock Mode L2CLK_OUTA L2CLK_OUTB L2SYNC_OUT L2 Differential Clock Mode L2CLK_OUTB L2CLK_OUTA L2SYNC_OUT PC755/745 30 Figure 8-5. t L2CLK ...
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... Guaranteed by design and characterization. 6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact your local Atmel sales office for more information. 2138G–HIREL–05/06 provides the L2 bus interface AC timing specifications for the PC755 as defined in and Figure 8-7 on page 32 32 ...
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Figure 8-6 shows the L2 bus input timing diagrams for the PC755. Figure 8-6. L2 Bus Input Timing Diagrams L2SYNC_IN L2 Data and Data Parity Inputs Figure 8-7 shows the L2 bus output timing diagrams for the PC755. Figure 8-7. ...
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Table 8-7. JTAG AC Timing Specifications (Independent of SYSCLK) Parameter (3) Input Setup Times Boundary scan data - TMS, TDI (3) Input Hold Times Boundary scan data - TMS, TDI (4) Valid Times Boundary ...
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Figure 8-11 Figure 8-11. TRST Timing Diagram Figure 8-12 Figure 8-12. Boundary-Scan Timing Diagram Data Outputs Data Outputs Figure 8-13 Figure 8-13. Test Access Port Timing Diagram PC755/745 34 provides the TRST timing diagram. VM TRST t TRST VM = ...
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JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to ...
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Figure 8-14. JTAG Interface Connection COP Connector Physical Pin Out Notes: The COP header shown in points, register and memory examination/modification and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated ...
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The COP interface has a standard header for connection to the target system, based on the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The con- nector typically has pin 14 removed as a connector key. Figure ...
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... Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. 9.2 Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-PRF-883 and guarantying the parameters not tested at tempera- ture extremes for the entire temperature range. ...
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Clock Relationship Choices The PC755’s PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) fre- quency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PC755 is ...
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The PC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the PC755. The divided-down clock is then phase-adjusted by an on- chip delay-lock-loop (DLL) circuit and should be routed from the ...
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System Design Information 10.1 PLL Power Supply Filtering The AV generation phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the power supplied to the AV the 500 kHz to 10 MHz resonant ...
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Decoupling Recommendations Due to the PC755’s dynamic power management feature, large address and data buses, and high operating frequencies, the PC755 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive ...
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Figure 10-3. Driver Impedance Measurement Circuit Alternately, the following is another method to determine the output impedance of the PC755. A voltage source, V low, the voltage source is set to a value that is equal to (L2 ...
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Table 10-1 acterized at 0°C, 65°C, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 10-1. Impedance 10.6 Pull-up Resistor Requirements The PC755 requires pull-up resistors (1 kΩ – 5 kΩ) on several ...
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... All new designs should allow for either ceramic or plastic BGA packages for this device. For more information on designing a common footprint for both plastic and ceramic package types, please contact your local Atmel sales office. 11.1 Package Parameters for the PC745 The package parameters are as provided in the following list. The package type is 21 × ...
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Mechanical Dimensions of the PC745 HiTCE Package Figure 11-1 PC745, 255 HiTCE package. Figure 11-1. Mechanical Dimensions and Bottom Surface Nomenclature of the PC745 HiTCE A1 CORNER 0 ...
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Mechanical Dimensions of the PC745 PBGA Package Figure 11-2 PC745, 255 PBGA package. Figure 11-2. Mechanical Dimensions and Bottom Surface Nomenclature of the PC745 PBGA A1 CORNER 0 ...
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Mechanical Dimensions of the PC755 PBGA Figure 11-3 PC755, 360 PBGA package. Figure 11-3. Mechanical Dimensions and Bottom Surface Nomenclature of the PC755 PBGA A1 CORNER 0 ...
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Mechanical Dimensions of the PC755 CBGA Package Figure 11-4 PC755, 360 CBGA package. Figure 11-4. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CBGA CORNER 0 ...
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Mechanical Dimensions of the PC755 HiTCE Package Figure 11-5 PC755, 360 HiTCE package. Figure 11-5. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (HiTCE CORNER 0 ...
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Mechanical Dimensions of the PC755 CI-CGA Package Figure 11-6 360 CI-CGA package. Figure 11-6. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CI-CGA CORNER 0 ...
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... For availability of the different versions, contact your local Atmel sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by Atmel. Reliability of a PCX part-number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes ...
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... Atmel customers using or selling these products for use in such applications their own risk and agree to fully indemnity Atmel for any damages resulting from such improper use or sale. 13.2 Differences with Commercial Part 14 ...
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Table of Contents Features .................................................................................................... 1 Description ............................................................................................... 1 Screening .................................................................................................. 2 1 General Description ................................................................................. 2 2 Pin Assignments ...................................................................................... 6 3 Signal Description ................................................................................. 13 4 Detailed Specifications .......................................................................... 14 5 Applicable Documents .......................................................................... 14 6 Thermal Characteristics ...
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Package Mechanical Data ..................................................................... 45 12 Ordering Information ............................................................................. 52 13 Definitions .............................................................................................. 53 14 Document Revision History .................................................................. 53 PC8280 [Preliminary] ii 10.4 Connection Recommendations ..........................................................................42 10.5 Output Buffer DC Impedance .............................................................................42 10.6 Pull-up Resistor Requirements ...........................................................................44 11.1 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...