TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 22

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 10-6.
11. Electrical Characteristics
11.1
11.2
Table 11-1.
Notes:
22
Signal Name
Transfer Start
Transfer Type
Write-through
Characteristics
Input High Voltage (all inputs except SYSCLK)
Input Low Voltage (all inputs except SYSCLK)
SYSCLK Input High Voltage
SYSCLK Input Low Voltage
Input Leakage Current
Hi-Z (off-state)
Leakage Current
Output High Voltage
Output Low Voltage
Capacitance, V
Capacitance, V
General Requirements
Static Characteristics
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. Capacitance is periodically sampled rather than 100% tested.
TSPC603R
Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued)
Electrical Characteristics with
IN
IN
= 0V, f = 1 MHz
= 0V, f = 1 MHz
Abbreviation
TS
TT[0-4]
WT
All static and dynamic electrical characteristics specified for inspection purposes and the rele-
vant measurement conditions are given below:
The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of
the PLL_CFG0 to PLL_CFG3 signals. All timings are respectively specified to the rising edge of
SYSCLK.
These specifications are for 166 MHz to 300 MHz processor core frequencies for CBGA 255,
HiTCE CBGA 255 and CI-CGA 255 packages and 166 MHz to 200 MHz processor core frequen-
cies for the Cerquad 240 package.
•
•
Table
Table
(2)
(2)
(excludes TS, ABB, DBB, and ARTRY)
(for TS, ABB, DBB, and ARTRY)
11-1: Static electrical characteristics for the electrical variants
11-2: Dynamic electrical characteristics for the 603R
Signal Function
If output, begun a memory bus transaction and the address bus and transfer
attribute signals are valid
If input, another master has begun a bus transaction and the address bus and
transfer attribute signals are valid for snooping (see GBL)
Type of transfer in progress
A single-beat transaction is write-through
V
DD
V
V
V
V
I
I
OH
OL
= A
IN
IN
IN
IN
= +7 mA
= 3.465V
= 5.5V
= 3.465V
= 5.5V
= -7 mA
V
DD
= 2.5V ±5%; O
(1)(3)
(1)(3)
(1)(3)
(1)(3)
V
DD
= 3.3 ±5%V, GND = 0V, -55°C ≤ T
Symbol
CV
CV
V
V
V
I
I
C
C
V
I
I
TSI
TSI
IN
IN
OH
OL
IH
IN
IN
IL
IH
IL
GND
GND
Min
2.4
2.4
2
-
-
-
-
-
-
-
Max
300
300
5.5
0.8
5.5
0.4
0.4
30
30
10
15
-
5410B–HIREL–09/05
C
≤ 125°C
Unit
µA
µA
µA
µA
Signal
Type
I/O
I/O
Output
pF
pF
V
V
V
V
V
V