ATF22V10C-7PX Atmel, ATF22V10C-7PX Datasheet - Page 7

• Manufacturer Part Number: ATF22V10C-7PX
• Description: IC EE PLD 500GATE 5V 7NS 24DIP
• Manufacturer: Atmel

Specifications of ATF22V10C-7PX

• Programmable Type: EE PLD
• Number Of Macrocells: 10
• Voltage - Input: 5V
• Speed: 7ns
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Family Name: ATF22V10C
• Process Technology: EECMOS
• # Macrocells: 10
• # I/os (max): 10
• Frequency (max): 166MHz
• Propagation Delay Time: 7.5ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

0735U–PLD–7/10
4.7
4.8
5.
6.
7.
Power-up Reset
The registers in the Atmel
V
output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how V
Figure 4-1.
Preload of Registered Outputs
The ATF22V10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Programming Hardware
and Software Support” for information on software/programming.
Table 7-1.
Parameter
t
V
CC
1. The V
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high
3. The clock must remain stable during t
POWER
REGISTERED
OUTPUTS
C LOCK
PR
RST
crossing V
CC
V
rise must be monotonic, and starts below 0.7V
Power-up Reset Timing
Programming/Erasing
R
RST
ST
Description
Power-up Reset Time
Power-up Reset Voltage
, all registers will be reset to the low state. The output state will depend on the polarity of the
CC
actually rises in the system, the following conditions are required:
®
t
ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from
PR
t
W
t
S
PR
Typ
600
3.8
Atmel ATF22V10C(Q)
1,000
Max
4.5
Units
ns
V
7