CS42526-CQZ Cirrus Logic Inc, CS42526-CQZ Datasheet - Page 13

• Manufacturer Part Number: CS42526-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42526-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/6 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1037

DS585F1
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, T
5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Notes:
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
R S T
S D A
S C L
17. Data must be held for sufficient time to bridge the transition time, t
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
A
-------------------- -
256
Stop
= -10 to +70° C; For DQZ, T
15
t
t
irs
×
buf
Fs
for Single-Speed Mode,
Start
Parameter
t
t
hdst
lo w
t
hdd
Figure 3. Control Port Timing - I²C Format
t
A
high
= -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to
-------------------- -
128 Fs
t sud
L
15
= 30 pF)
×
(Note 17)
(Note 18)
t ack
for Double-Speed Mode,
Symbol
t
t
t
t
t
t
t
susp
t
t
f
hdst
high
sust
t
hdd
sud
low
t
t
ack
buf
scl
irs
rc
fc
R e p e a te d
t sust
Sta rt
fc
, of SCL.
Min
500
250
4.7
4.0
4.7
4.0
4.7
4.7
0
-
-
-
-
t
hdst
----------------- -
64 Fs
t rd
15
×
t rc
for Quad-Speed Mode
(Note 19)
t fc
Max
100
300
1
-
-
-
-
-
-
-
-
-
t fd
CS42526
Stop
t susp
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
13