CS42528-CQZ Cirrus Logic Inc, CS42528-CQZ Datasheet - Page 33

• Manufacturer Part Number: CS42528-CQZ
• Description: IC CODEC S/PDIF RCVR 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: General Purposer

Specifications of CS42528-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 114 / 114
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/8 DAC
• Thd Plus Noise: - 100 dB ADC / - 100 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1503 - BOARD EVAL FOR CS42528/CS49300
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1038

DS586F1
4.6.4
Functional Mode Register (addr = 03h)
Interface Format Register (addr = 04h)
Misc. Control Register (addr = 05h)
Set CODEC_FMx = SAI_FMx = 00,01,10
Set ADC_SP SELx = 00
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Set DAC_OLx bits = 00,01,10
Set CODEC_SP M/S = 1
Set SAI_SP M/S = 1
Set EXT ADC SCLK = 0
ADC Mode
4.6.4.1
One-Line Mode Configuration #1 can support up to 8 channels of DAC data, 6 channels of ADC data and
2 channels of S/PDIF received data. This is the only configuration which will support up to 24-bit samples
at a sampling frequency of 48 kHz on all channels for both the DAC and ADC.
Register / Bit Settings
One-Line Mode (OLM) Configurations
Line Mode
Not One-
One-Line
One-Line
Mode #1
Mode #2
OLM Config #1
CS5361
CS5361
SDOUT1
SDOUT2
CX_SCLK=64 Fs
CX_LRCK=SSM/DSM/QSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
SCLK
MCLK
LRCK
Not One-Line Mode
Figure 16. OLM Configuration #1
RMCK
ADCIN1
ADCIN2
CS42528
CX_LRCK must equal SAI_LRCK; sample rate conversion not supported
Select ADC operating mode, see table below for valid combinations
Select DAC operating mode, see table below for valid combinations
Configure ADC data on CX_SDOUT, S/PDIF data on SAI_SDOUT
SAI_SDOUT
CX_SDOUT
SAI_LRCK
SAI_SCLK
CX_SDIN1
CX_SDIN2
CX_SDIN3
CX_SDIN4
Select the digital interface format when not in One-Line Mode
CX_SCLK
CX_LRCK
Configure Serial Audio Interface Port to master mode.
Identify external ADC clock source as SAI Serial Port.
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
CX_SCLK=128 Fs
CX_LRCK=SSM/DSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
Configure CODEC Serial Port to master mode.
SPDIF Data
64Fs,128Fs, 256Fs
ADC Data
One-Line Mode #1
DAC Mode
64Fs
not valid
SDIN_PORT1
MCLK
SCLK_PORT1
LRCK_PORT1
SCLK_PORT2
LRCK_PORT2
SDIN_PORT2
SCLK_PORT3
LRCK_PORT3
SDOUT1_PORT3
SDOUT2_PORT3
SDOUT3_PORT3
SDOUT4_PORT3
Description
DIGITAL AUDIO
PROCESSOR
CX_SCLK=256 Fs
CX_LRCK=SSM
SAI_SCLK=64 Fs
SAI_LRCK=CX_LRCK
One-Line Mode #2
not valid
not valid
CS42528
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