MAX9851ETM+ Maxim Integrated Products, MAX9851ETM+ Datasheet - Page 30

• Manufacturer Part Number: MAX9851ETM+
• Description: IC CODEC AUDIO STEREO 48TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9851ETM+

• Data Interface: Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 81.5 / 88
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 87.5
• Voltage - Supply, Analog: 2.6 V ~ 3.3 V
• Voltage - Supply, Digital: 1.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Number Of Adc Inputs: 3
• Number Of Dac Outputs: 3
• Conversion Rate: 48 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C)
• Resolution: 18 bit
• Operating Supply Voltage: 1.7 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Supply Current: 6.2 mA
• Thd Plus Noise: - 84 .5 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
Set S1MAS or S2MAS to 1 (register 0x04 or 0x06, bit B7)
to operate the respective interface in master mode. The
MAX9851/MAX9853 generate the LRCLK and BCLK sig-
nals, which can be used to send and receive digital
audio samples. In stereo audio mode, the BCLK signal is
a pulse with a period of 310ns. BCLK is inactive when
there are no bits transmitted on SDIN or SDOUT. The
number of clock cycles per frame is equal to the config-
ured bit depth. Set S1MAS or S2MAS to 0 to operate the
respective interface in slave mode, and disable the ADC
in stereo audio modes (slave mode not available). The
interface accepts slave mode noninteger sample clocks
ranging from 8kHz to 48kHz and the appropriate bit
clocks in these DAC-only stereo audio modes. See
Figure 4 for the digital audio interface timing diagrams.
In master voice mode, the S1 digital audio interface
operates as shown in Figure 3. The BCLK signal is a
continuous 13MHz clock. The LRCLK consists of a sin-
gle-pulse frame sync signal rather than the left-/
right-frame sync clock method used in I
the 8kHz voice mode can be run from either the 13MHz
or 26MHz MCLK frequency, 16kHz voice mode
requires a 26MHz MCLK. Although both S1 and S2
interfaces are capable of operating in voice mode, only
the primary S1 interface can be configured with a
bandpass voice filter.
Table 1. Digital Audio Interface Modes
*26MHz clock required for synchronous 16kHz sample rate.
30
11.025
8 to 48
22.05
______________________________________________________________________________________
44.1
48
32
24
16
12
16
16
8
8
8
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Master (stereo audio mode)
Slave (stereo audio mode)
MODE
Master (voice mode)
Master (voice mode)
Slave (voice mode)
Slave (voice mode)
Stereo Audio Modes
Voice Modes
2
S. Although
In slave voice mode, an external device must provide
at least 16 BCLK cycles following an LRCLK pulse,
which will allow operation using any BCLK rate or oper-
ation with BCLK shut off between word transfers.
In voice mode, the first 16 bits of each sample treated
as left-channel audio data. The MAX9851/
MAX9853 are capable of receiving up to 16 additional
bits per sample word, treated as right-channel data.
These additional bits are routed to the Vibe circuitry
when operating in voice mode on the S1 interface.
When operating on the S2 interface, these additional
bits are interpreted as right-channel data, optionally
routed to the right DAC and the Vibe circuitry.
Included in each digital audio interface is a timing con-
trol module allowing the MAX9851/MAX9853 to gener-
ate the clock signals for master mode.
The two digital audio interfaces include full functionality
for I
justified data, and either inverted LRCLK or inverted
BCLK. Set S1MODE or S2MODE to 0xA or 0xB (register
0x03 or 0x05, bits B3–B0) to configure the interface for
8kHz or 16kHz voice mode, respectively.
Set S1MNO or S2MNO to 1 (register 0x03 or 0x05, bit
B5) to mix the right- and left-channel input data to cre-
ate a mono serial data signal from the left and right
input data. The result is then input to the left digital filter
path, leaving the right path unused. The output of the
left filter path can still be sent to either or both the left
f
S
2
(ADC ON) (kHz)
S modes of operation, including true I
16.000*
16.000*
47.794
43.333
31.863
24.074
21.959
15.931
12.037
11.054
8.025
8.000
8.000
—
f
S
Additional Features
(ADC OFF) (kHz)
48.0011
44.0989
31.9986
23.9990
22.0494
15.9993
12.0010
11.0247
16.000*
16.000*
7.9997
8 to 48
8.000
8.000
2
S data, left-