CS42436-CMZ Cirrus Logic Inc, CS42436-CMZ Datasheet - Page 21

• Manufacturer Part Number: CS42436-CMZ
• Description: IC CODEC 108DB 192KHZ 52-MQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42436-CMZ

• Package / Case: 52-MQFP, 52-PQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 6
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/6 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1612

DS647F2
SWITCHING SPECIFICATIONS - ADC/DAC PORT
(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C
Notes:
Slave Mode
RST pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (FS pin)
SCLK Duty Cycle
SCLK High Time
SCLK Low Time
FS Rising Edge to SCLK Rising Edge
SCLK Rising Edge to FS Falling Edge
DAC_SDIN Setup Time Before SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
DAC_SDIN Hold Time After SCLK Rising Edge
ADC_SDOUT Hold Time After SCLK Rising Edge
ADC_SDOUT Valid Before SCLK Rising Edge
17. After powering up the CS42436, RST should be held low after the power supplies and clocks are settled.
18. See
19. VLS is limited to nominal 2.5 V to 5.0 V operation only.
20. ADC does not meet timing specification for Quad-Speed Mode.
DAC_SDIN
ADC_SDOUT
SCLK
(input)
(input)
FS
Table 7 on page 43
Parameters
t
fss
Double-Speed Mode
Figure 5. TDM Serial Audio Interface Timing
Quad-Speed Mode
for suggested MCLK frequencies.
Single-Speed Mode
t
MSB
fsh
(Note 17)
(Note 18)
(Note 19)
(Note 20)
LOAD
t
ds
= 15 pF.)
t
Symbol
dh2
t
t
t
t
t
sckh
t
t
dval
sckl
t
t
dh1
dh2
F
F
F
fss
fsh
ds
dh
t
sckh
s
s
s
MSB
t
dh1
0.512
Min
t
MSB-1
100
45
50
45
16
10
15
dval
1
4
8
8
5
3
5
5
t
sckl
MSB-1
Max
100
200
50
55
50
55
-
-
-
-
-
-
-
-
-
-
CS42436
Units
MHz
kHz
kHz
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
21