CS42438-DMZ Cirrus Logic Inc, CS42438-DMZ Datasheet
CS42438-DMZ
Specifications of CS42438-DMZ
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CS42438-DMZ Summary of contents
Page 1
... An auxiliary serial input is available for an additional two channels of PCM data. The CS42438 is available in a 52-pin MQFP package in Commercial (-10°C to +70°C) and Automotive (-40°C to +105°C) grades. The CDB42438 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please refer to Information” ...
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... CODEC Digital Interface ................................................................................................................. 33 5.5.1 TDM ................................................................................................................................. 33 5.5.2 I/O Channel Allocation ........................................................................................................... 34 5.6 AUX Port Digital Interface Formats ................................................................................................ 34 5.6.1 Hardware Mode ..................................................................................................................... 34 5.6.2 Software Mode ...................................................................................................................... 34 5.6.3 I²S .......................................................................................................................................... 34 5.6.4 Left-Justified .......................................................................................................................... 35 5.7 Control Port Description and Timing ............................................................................................... 35 5.7.1 SPI Mode ............................................................................................................................... 35 5.7.2 I²C Mode ................................................................................................................................ 36 2 ....................................................................................... 9 CS42438 DS646F2 ...
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... Invert Signal Polarity (INV_AINX) ........................................................................................ 49 7.13 Status (Address 19h) (Read Only) ............................................................................................... 49 7.13.1 CLOCK ERROR (CLK ERROR) .......................................................................................... 49 7.13.2 ADC Overflow (ADCX_OVFL) ............................................................................................. 49 7.14 Status Mask (Address 1Ah) .......................................................................................................... 49 8. EXTERNAL FILTERS ........................................................................................................................... 50 8.1 ADC Input Filter .............................................................................................................................. 50 8.1.1 Passive Input Filter ............................................................................................................. 51 8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 52 DS646F2 .......................................................................... 47 CS42438 3 ...
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... Figure 34.SSM Stopband Rejection .......................................................................................................... 56 Figure 35.SSM Transition Band ................................................................................................................ 56 Figure 36.SSM Transition Band (detail) .................................................................................................... 56 Figure 37.SSM Passband Ripple .............................................................................................................. 56 Figure 38.DSM Stopband Rejection .......................................................................................................... 56 Figure 39.DSM Transition Band ................................................................................................................ 56 Figure 40.DSM Transition Band (detail) .................................................................................................... 57 Figure 41.DSM Passband Ripple .............................................................................................................. 57 Figure 42.QSM Stopband Rejection ......................................................................................................... 57 4 CS42438 DS646F2 ...
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... Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Configurable Settings ................................................................................................. 26 Table 3. AIN5 Analog Input Selection ....................................................................................................... 29 Table 4. AIN6 Analog Input Selection ....................................................................................................... 29 Table 5. MCLK Frequency Settings .......................................................................................................... 33 Table 6. Serial Audio Interface Channel Allocations ................................................................................. 34 Table 7. MCLK Frequency Settings .......................................................................................................... 43 Table 8. Example AOUT Volume Settings ................................................................................................ 47 Table 9. Example AIN Volume Settings .................................................................................................... 48 DS646F2 CS42438 5 ...
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... DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data. Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active AUX_LRCK 15 on the Auxiliary serial audio data line CS42438 Pin Description 8. “Digital I/O Pin Characteristics” on page CS42438 40 39 AIN1+ 38 AIN1 AGND 34 AOUT8- 33 AOUT8+ 32 AOUT7+ 31 AOUT7- 30 AOUT6- 29 AOUT6+ 28 AOUT5+ 27 ...
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... AIN6 A,B 52,51 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir- FILT+ 47 cuits. DS646F2 CS42438 Sections 7.6.6-7.6.8 7 ...
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... Digital I/O Pin Characteristics Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Pin Name I/O Rail SW/(HW) ...
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... DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data. DS646F2 CS42438 Pin Description (Input) - Allows selection between the A and B single-ended inputs of 8. “Digital I/O Pin Characteristics” on page CS42438 40 AIN1 AIN1 AGND AOUT8 AOUT8+ 32 AOUT7+ AOUT7- 31 AOUT6- 30 AOUT6+ ...
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... AIN6 A,B 52,51 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir- FILT+ 47 cuits. 10 CS42438 Sections 7.6.6-7.6.8 DS646F2 ...
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... AD1/CDIN 3 AD0/ VLC FILT+ DGND DGND AGND AGND Connect DGND and AGND at Codec CS42438 +3 µF 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter Analog Output Filter 2 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter Input ...
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... AIN6_MUX 4 ADC3_HPF 3 MFREQ 6 VLC FILT+ DGND DGND AGND AGND Connect DGND and AGND at Codec CS42438 +3 µF 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter 2 Analog Output Filter Input ...
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... Symbol Analog VA Digital VD Serial Port Interface VLS Control Port Interface VLC (Note (Note Serial Port Interface V IND-S Control Port Interface V IND stg CS42438 Min Max Units 3.14 5.25 V 3.14 3.47 V 1.71 5.25 V 1.71 5.25 V °C -10 +70 °C -40 +105 Min Max Units -0 ...
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... VD = VLS = VLC = 3.3 V±5 V±5%; A Figure 20 on page 50 Differential Min Typ Max 99 105 - 96 102 - - -98 -92 - - ±100 - 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59* CS42438 and Figure 21 on page 50; Single-Ended Min Typ Max Unit 96 102 - - ±100 - ppm/°C Vpp kΩ ...
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... VD = VLS = VLC = 3.3 V±5 V±5%; A Figure 20 on page 50 Differential Min Typ Max 97 105 - 94 102 - - -98 -90 - - ±100 - 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60* CS42438 and Figure 21 on page 50; Single-Ended Min Typ Max Unit 94 102 - - ±100 - ppm/°C Vpp kΩ ...
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... Filter Settling Time Notes: 9. Filter response is guaranteed by design. 10. Response is clock-dependent and will scale with Fs. Note that the response plots been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16 (Notes 9, 10) to -0.1 dB corner to -0.1 dB corner CS42438 Min Typ Max Unit 0 - 0.4896 Fs ...
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... Min Typ Max 102 108 - 99 105 - - -98 - -36 - 100 - 1.235•VA 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA - 0.1 0.25 - ±100 - - 100 - - - 100 CS42438 and active filter in Single-Ended Min Typ Max Unit 99 105 - dB 96 102 - - 100 - dB Vpp - 0.1 0.25 ...
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... Figure 3. R and C reflect the recommended minimum resistance and L L for a recommended output filter. CS42438 and Figure 26 on page 54; Measure- Single-Ended Min Typ Max Unit 97 105 - dB 94 102 - ...
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... DAC1-4 3.3 µF + AOUTxx R L AGND Figure 3. Output Test Circuit for Maximum Load DS646F2 125 100 75 Analog Output 2 Figure 4. Maximum Loading CS42438 Safe Operating Region Ω ) Resistive Load -- ...
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... Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 16. De-emphasis is only available in Single-Speed Mode. 20 (Notes 9, 14) to -0.05 dB corner corner (Note 15 kHz Fs = 44.1 kHz kHz to -0.1 dB corner corner (Note 15) to -0.1 dB corner corner (Note 15) CS42438 Min Typ Max 0 - 0.4780 0 - 0.4996 -0.2 - +0.08 0.5465 - - ...
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... ADC_SDOUT Hold Time After SCLK Rising Edge ADC_SDOUT Valid Before SCLK Rising Edge Notes: 17. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled. 18. See Table 7 on page 43 19. VLS is limited to nominal 2 5.0 V operation only. ...
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... AUX_SDIN Setup Time Before SCLK Rising Edge AUX_SDIN Hold Time After SCLK Rising Edge AUX_LRCK AUX_SCLK AUX_SDIN Figure 6. Serial Audio Interface Slave Mode Timing 22 Symbol Min All Speed Modes lcks lcks sckh sckl MSB-1 MSB CS42438 Max Units - LRCK kHz · LRCK kHz DS646F2 ...
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... Figure 7. Control Port Timing - I²C Format CS42438 = 30 pF) L Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µ ...
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... CS t css CCLK CDIN CDOUT 24 Symbol f sck t srs t css t csh t scl t sch t dsu (Note 23 (Note 24 (Note 24 sch scl dsu MSB t pd MSB Figure 8. Control Port Timing - SPI Format CS42438 Min Max 100 - 100 f2 t csh pF) L Units MHz ns ns μ ...
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... kHz PSRR 60 Hz Symbol Serial Port VLS-1.0 Control Port V VLC-1.0 OH Serial Port V Control Port OL Serial Port 0.7xVLS Control Port V 0.7xVLC IH Serial Port Control Port for serial and control port power rails. CS42438 Min Typ Max Units - 60 600 850 1. 0.5•VA ...
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... PCM data on the ADC_SDOUT data line in the TDM digital interface format. See Digital Interface Formats” on page 34 The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined automatically based on the MCLK frequency setting. Single-Speed Mode (SSM) supports in- put sample rates kHz and uses a 128x oversampling ratio ...
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... Analog Inputs 5.2.1 Line-Level Inputs AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2. Figure 9 on page 28 shows the full-scale analog input levels. The CS42438 also accommodates single- ended signals on all inputs, AIN1-AIN filters. 5.2.1.1 Hardware Mode AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode ...
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... V PP RMS Figure 9. Full-Scale Input Single-Ended Input Filter Single-Ended Input Filter Differential Input Filter Differential Input Filter 51 VQ Single-Ended Input Filter Single-Ended Input Filter Figure 10. ADC3 Input Topology CS42438 5 AINx+ AINx- ADC3 AIN5_MUX ADC3 SINGLE AIN5 - 0 1 AIN6_MUX AIN6 - 0 1 DS646F2 ...
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... DC offset will continue to be subtracted from the conversion re- sult. This feature makes it possible to perform a system DC offset calibration by: 1. Running the CS42438 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. ...
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... After an approximate 2000 sample period delay, normal operation begins. 5.3.2 Line-Level Outputs and Filtering The CS42438 contains on-chip buffer amplifiers capable of producing line-level differential as well as sin- gle-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approxi- mately VQ. ...
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... LRCK delay Yes RST = Low Normal Operation VA/2. 2. Aout bias = VA/2. ERROR: Power removed 3. Audio signal generated per register settings. ERROR: MCLK/LRCK ratio change CS42438 Power-Down VA/2. Yes 2. Aout bias = Hi-Z. PDN bit = '1' audio signal generated. 4. Control Port Registers retain settings. ...
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... Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits. 5.3.4 De-Emphasis Filter The CS42438 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re- sponse is shown in Figure that utilize 50/15 μs pre-emphasis equalization as a means of noise reduction. ...
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... Figure 13. De-Emphasis Curve Description SSM 256 512 Table 5. MCLK Frequency Settings 43. FS identifies the start of a new frame and is equal to the sample rate, Fs. CS42438 µs Frequency Table 5 for the required frequen- Ratio (xFs) DSM QSM N/A N/A 256 N/A “ ...
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... Analog Output/Input Channel Allocation Format AOUT 1,2,3,4,5,6,7,8 ,5,6AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN) Table 6. Serial Audio Interface Channel Allocations Figure 18 on page 36 for timing relationship between AUX_LRCK and Figure 15. AUX I²S Format CS42438 LSB MSB LSB MSB LSB MSB AOUT6 AOUT7 AOUT8 ...
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... The control port has two modes: SPI and I²C, with the CS42438 acting as a slave device. SPI Mode is se- lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state ...
Page 36
... CS42438 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42438, the chip address field, which is the first byte sent to the CS42438, should match 10010 followed by the settings of the AD1 and AD0 ...
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... During the Hardware Mode power-up sequence, there must be no transitions on any of the hard- ware control pins. DS646F2 STOP MAP BYTE CHIP ADDRESS (READ INCR ACK START Figure 19. Control Port Timing, I²C Read Table 2 on page 26 CS42438 DATA DATA +1 DATA + n 0 AD1 AD0 ACK ACK NO ACK according to the Hardware Mode control STOP 37 ...
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... The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42438 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µ ...
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... AOUT6 AOUT6 AOUT6 VOL6 VOL5 VOL4 AOUT7 AOUT7 AOUT7 VOL6 VOL5 VOL4 AOUT8 AOUT8 AOUT8 VOL6 VOL5 VOL4 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1 CS42438 Rev_ID3 Rev_ID2 Rev_ID1 PDN_DAC2 PDN_DAC1 MFreq2 MFreq1 MFreq0 Reserved Reserved Reserved ADC2 ADC3 AIN5_MUX SINGLE SINGLE ...
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... VOL5 VOL4 AIN6 AIN6 AIN6 VOL6 VOL5 VOL4 INV_A6 INV_A5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved CS42438 AIN1 AIN1 AIN1 VOL3 VOL2 VOL1 AIN2 AIN2 AIN2 VOL3 VOL2 VOL1 AIN3 AIN3 AIN3 VOL3 VOL2 VOL1 AIN4 AIN4 AIN4 VOL3 VOL2 ...
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... Chip I.D. and Revision Register (Address 01h) (Read Only Chip_ID3 Chip_ID2 Chip_ID1 7.2.1 Chip I.D. (CHIP_ID[3:0]) Default = 0000 Function: I.D. code for the CS42438. Permanently set to 0000. 7.2.2 Chip Revision (REV_ID[3:0]) Default = 0001 Function: CS42438 revision level. Revision A is coded as 0001. DS646F2 ...
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... DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts. 7.3.3 Power Down (PDN) Default = Disable 1 - Enable Function: The entire device will enter a low-power state when this function is enabled. The contents of the control registers are retained in this mode PDN_DAC3 PDN_DAC4 CS42438 PDN_DAC2 PDN_DAC1 PDN DS646F2 ...
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... MHz to 12.8000 MHz 0 1 1.5360 MHz to 19.2000 MHz 0 2.0480 MHz to 25.6000 MHz 1 3.0720 MHz to 38.4000 MHz X 4.0960 MHz to 51.2000 MHz Table 7. MCLK Frequency Settings Reserved Reserved CS42438 MFreq1 MFreq0 Reserved Ratio (xFs) SSM DSM QSM 256 N/A N/A 384 N/A ...
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... ADC. See 7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) Default = Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2 ADC1 ADC2 SINGLE SINGLE 16. Figure 21 on page 50 CS42438 ADC3 AIN5_MUX AIN6_MUX SINGLE “ADC Digital Filter “ADC Digital Filter Characteris- for a graphical description. DS646F2 ...
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... Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) Default = 0 Function: DS646F2 Figure 21 on page 50 Figure 12 on page 32 Figure 12 on page 32 Figure 12 on page AMUTE MUTE ADC_SP CS42438 for a graphical description. and Figure 21 on page 50 for graphical for a graphical description. for a graphical description ADC_SNGVOL ADC_SZC1 ADC_SZC0 ...
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... Enabled Function: The Digital-to-Analog converters of the CS42438 will mute the output following the reception of 8192 con- secutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained during the mute period ...
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... Default = Disabled 1 - Enabled Function: The respective Digital-to-Analog converter outputs of the CS42438 will mute when enabled. The quies- cent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero Cross bits (DAC_SZC[1:0]). 7.9 AOUTX Volume Control (Addresses 08h- 0Fh) ...
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... Table 9. Example AIN Volume Settings CS42438 INV_AOUT3 INV_AOUT2 INV_AOUT1 AINx_VOL2 AINx_VOL1 AINx_VOL0 Table DS646F2 ...
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... Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active during the error condition. See 7.13.2 ADC Overflow (ADCX_OVFL) Default = x Function: Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of the associated ADC’s. 7.14 Status Mask (Address 1Ah) 7 ...
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... VA 470 pF C0G 100 kΩ Ω 4.7 μF + 2700 pF 100 kΩ Figure 21. Single-Ended Active Input Filter CS42438 Figures 20 and 23 for low-cost, low-component- ADC1-3 AINx+ 2700 pF C0G AINx- ADC1-2 AIN1+,2+,3+,4+ C0G AIN1-,2-,3-,4- ADC3 AIN5A,6A ...
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... Figure 22 illustrates the unity gain, passive input filter solution. 10 μF 150 Ω 2700 pF 100 kΩ C0G 4.7 μF 10 μF 150 Ω 2700 pF C0G 10 μF 150 Ω 2700 pF C0G Figure 22. Passive Input Filter CS42438 ADC1-2 AIN1+,2+,3+,4+ AIN1-,2-,3-,4- ADC3 AIN5A,6A AIN5B,6B 51 ...
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... Figure 23. Passive Input Filter w/Attenuation 52 ADC1-2 10 μF 2.5 kΩ AIN1+,2+,3+,4+ Ω 2700 pF 2.5 k C0G AIN1-,2-,3-,4- 4.7 μF ADC3 10 μF 2.5 kΩ AIN5A,6A Ω 2700 pF 2.5 k C0G 10 μF 2.5 kΩ AIN5B,6B Ω 2700 pF 2.5 k C0G CS42438 Figure 23, the input DS646F2 ...
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... C0G Figure 24. Active Analog Output Filter 560 Ω 3.3 µ kΩ Figure 25. Passive Analog Output Filter CS42438 C0G 22 μF 562 Ω 47.5 k Ω C0G C R ext R + 560 ext πF R 560 ...
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... Figure 31. DSM Transition Band CS42438 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (normalized to Fs) 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) DS646F2 0 ...
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... Frequency (normalized to Fs) Figure 32. DSM Transition Band (Detail) DS646F2 0.50 0.51 0.52 Figure 33. DSM Passband Ripple CS42438 . que ncy (norm alize .50 55 ...
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... Figure 36. SSM Transition Band (detail) Figure 38. DSM Stopband Rejection 56 Figure 35. SSM Transition Band 0.05 0 -0.05 -0. 1 -0.15 -0. 2 -0.25 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Frequency (normalized to Fs) Figure 37. SSM Passband Ripple Figure 39. DSM Transition Band CS42438 0.4 0.45 0.5 DS646F2 ...
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... Figure 43. QSM Transition Band 0 - -1. 5 0.6 0.65 0.7 0 Figure 45. QSM Passband Ripple CS42438 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency (normalized to Fs) 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency(normalized to Fs) 0.05 ...
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... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 58 CS42438 DS646F2 ...
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... Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 7. Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range Fujimori, K. Ha- mashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, Oc- tober 1992. 8. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com DS646F2 CS42438 59 ...
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... Nominal pin pitch is 0.65 mm Controlling dimension is mm. JEDEC Designation: MS022 Symbol 2 Layer Board 4 Layer Board CS42438 A A1 MILLIMETERS MIN NOM --- --- 0.00 --- 0.22 --- --- 13.20 BSC --- 10.00 BSC --- 13.20 BSC --- 10.00 BSC --- ...
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... YES Automotive -40°C to +105° Changes “Recommended Operating Conditions” on page and “Analog Input Characteristics (Automotive)” on page www.cirrus.com. CS42438 Temp Range Container Order # Rail CS42438-CMZ Tape & Reel CS42438-CMZR Rail CS42438-DMZ Tape & Reel CS42438-DMZR - - CDB42438 13. “Analog Input Characteris- 15. 61 ...