MAX9867ETJ+ Maxim Integrated Products, MAX9867ETJ+ Datasheet - Page 26

• Manufacturer Part Number: MAX9867ETJ+
• Description: IC STEREO AUD CODEC LP 32TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: Stereo Audior

Specifications of MAX9867ETJ+

• Data Interface: I²C, Serial
• Resolution (bits): 18 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 1.65 V ~ 1.95 V
• Voltage - Supply, Digital: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ultra-Low Power Stereo Audio Codec
The MAX9867’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1–4 for timing diagrams. In master
mode, the MAX9867 outputs LRCLK and BCLK, while in
slave mode they are inputs. When operating in master
Table 6. Digital Audio Interface Registers
26
Interface Mode
Interface Mode
______________________________________________________________________________________
SDODLY
LVOLFIX
HIZOFF
REGISTER
BITS
MAS
WCI
DLY
BCI
Master Mode
0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
Note: WCI is ignored when TDM = 1.
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK.
SDOUT transitions after the rising edge of BCLK as determined by SDODLY.
1 = SDIN is latched into the part on the falling edge of BCLK.
SDOUT transitions after the falling edge of BCLK as determined by SDODLY.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
SDOUT Delay
0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.
1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.
See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).
Delay Mode
0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.
1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
Note: DLY is ignored when TDM = 1.
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867,
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.
Note: High-impedance mode is intended for use when TDM = 1.
See the Line Inputs section.
following an LRCLK edge (I
allowing SDOUT to be shared by other devices.
MAS
Digital Audio Interface
B7
0
WCI
B6
0
2
BCI
S-compatible mode).
B5
0
LVOLFIX
DLY
B4
mode, BCLK can be configured in a number of ways to
ensure compatiblity with other audio devices.
LVOLFIX is used to fix the line input playback volume to
0dB regardless of VOLL and VOLR. See the Line Inputs
section for complete details and Table 6.
FUNCTION
DMONO
HIZOFF
B3
TDM
B2
BSEL
B1
0
B0
0
REGISTER
ADDRESS
0x08
0x09