AD1837AAS Analog Devices Inc, AD1837AAS Datasheet
AD1837AAS
Specifications of AD1837AAS
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AD1837AAS Summary of contents
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FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-, 20-, 24-Bit Word Lengths Multibit - Modulators with Perfect Differential ...
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AD1837A–SPECIFICATIONS TEST CONDITIONS Supply Voltages (AVDD, DVDD) 5.0 V Ambient Temperature 25∞C Input Clock 12.288 MHz, (256 ADC Input Signal 1.0078125 kHz, –1 dBFS (Full Scale) DAC Input Signal 1.0078125 kHz, 0 dBFS (Full Scale) Input Sample Rate (f ) ...
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Parameter ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple ...
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AD1837A TIMING SPECIFICATIONS Parameter MASTER CLOCK AND RESET t MCLK High MH t MCLK Low ML PD/RST Low t PDR ® SPI PORT t CCLK High CCH t CCLK Low CCL t CCLK Period CCP t CDATA Setup CDS t ...
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Parameter TDM256 MODE (Master, 48 kHz and 96 kHz) t BCLK Delay TBD t FSTDM Delay FSD t ASDATA Delay TABDD t DSDATA1 Setup TDDS t DSDATA1 Hold TDDH TDM256 MODE (Slave, 48 kHz and 96 kHz) f BCLK Frequency ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Model AD1837AAS AD1837AAS-REEL AD1837AASZ* AD1837AASZ-REEL* EVAL-AD1837AEB * free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1837A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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DVDD CLATCH CIN PD/RST AGND NC OUTL1 NC OUTR1 AGND AVDD NC OUTL2 CONNECT Pin Number Mnemonic 1, 39 DVDD 2 CLATCH 3 CIN PD/RST 4 5, 10, 16, 24, 30, 35 AGND 6, 12, 25, 31 ...
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AD1837A –Typical Performance Characteristics 0 –50 –100 –150 0 5 FREQUENCY – Normalized to TPC 1. ADC Composite Filter Response 5 0 –5 –10 –15 –20 –25 – FREQUENCY – Hz TPC 2. ADC High-Pass Filter Response, ...
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FREQUENCY – kHz TPC 7. DAC Composite Filter Response, f 0.10 0.05 0 –0.05 –0. FREQUENCY – kHz TPC 8. DAC Composite Filter Response, f (Pass-Band Section) REV. A 0.2 ...
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AD1837A TERMINOLOGY Dynamic Range The ratio of a full-scale input signal to the integrated input noise in the pass band ( kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and ...
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FUNCTIONAL OVERVIEW ADCs There are two ADC channels in the AD1837A, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate kHz. The ADCs include on-board ...
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AD1837A DAC INPUT CLOCK SCALING 1 MCLK 2 12.288MHz 2/3 ADC OUTPUT t CLS t CLATCH CCP CCLK CIN D15 D14 t COUT COE DAC outputs if the jitter spectrum contains large spectral peaks highly recommended that the ...
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Control Register 2, the serial mode can be changed to right- justified (RJ), left-justified DSP (DSP), or left-justified (LJ). In the RJ mode necessary to set Bits 4 and 5 to define the width of the data-word. The ...
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AD1837A ABCLK t ABL t ALS ALRCLK ASDATA LEFT-JUSTIFIED MSB MODE ASDATA COMPATIBLE MODE ASDATA RIGHT-JUSTIFIED MODE t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA ...
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LRCLK BCLK ADC DATA LRCLK BCLK ADC DATA LRCLK BCLK DAC DATA LRCLK BCLK DAC DATA REV. A 128 BCLKs 16 BCLKs SLOT 1 SLOT 5 SLOT 2 SLOT 3 SLOT 4 SLOT 6 LEFT RIGHT MSB MSB – 1 ...
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AD1837A t ABH ABCLK t ABL t ALS ALRCLK t ALH ASDATA MSB Figure 9. ADC Packed Mode Timing DBCLK DLRCLK t ABDD DSDATA MSB – 1 –16– t DBH t DBL t DLS t DLH t DDS MSB MSB ...
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Pin Name I ASDATA (O) I DSDATA1 (I) I DSDATA2 (I)/AAUXDATA1 (I) I DSDATA3 (I)/AAUXDATA2 (I) I DSDATA4 (I)/AAUXDATA3 (I) I ALRCLK (O) LRCLK for ADC ABCLK (O) BCLK for ADC DLRCLK (I)/AUXLRCLK (I/O) LRCLK In/Out Internal DACs DBCLK (I)/AUXBCLK ...
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AD1837A LRCLK ADC BCLK NO. 1 DATA SLAVE MCLK LRCLK ADC BCLK NO. 2 DATA SLAVE MCLK LRCLK ADC BCLK NO. 3 DATA SLAVE MCLK Figure 12. Auxiliary Mode Connection (Master Mode) to SHARC LRCLK ADC BCLK NO. 1 DATA ...
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CONTROL/STATUS REGISTERS The AD1837A has 15 control registers which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each ...
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AD1837A Register Address Register Name Description 0000 DACCTRL1 0001 DACCTRL2 0010 DACVOL1 0011 DACVOL2 0100 DACVOL3 0101 DACVOL4 0110 DACVOL5 0111 DACVOL6 1000 DACVOL7 1001 DACVOL8 1010 ADCPeak0 1011 ADCPeak1 1100 ADCCTRL1 1101 ADCCTRL2 1110 ADCCTRL3 1111 Reserved R/W W ...
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Table VIII. DAC Volume Control Address R/W RES DAC Volume 15, 14, 13 0010 = DACL1 0 0 0000000000 = Mute 0011 = DACR1 0000000001 = 1/1023 ...
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AD1837A CASCADE MODE Dual AD1837A Cascade The AD1837A can be cascaded to an additional AD1837A, which, in addition to six external stereo ADCs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade ...
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F 600Z 5.76k 5.76k AUDIO + INPUT 120pF NPO 100pF NPO 237 OP275 V REF 5.76k 5.76k 750k 237 OP275 V REF Figure 16. Typical ADC Input Filter Circuit REV BIAS (2.25V) ADCxN 11k 1nF NPO 100pF ...
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AD1837A 10 6 2.20 2 2.00 1.80 0.25 MAX Revision History Location 1/04—Data Sheet changed from REV REV. A. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . ...