W6811IW Nuvoton Technology Corporation of America, W6811IW Datasheet - Page 6

• Manufacturer Part Number: W6811IW
• Description: IC VOICEBAND CODEC 5V/3V 24TSSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Type: PCMr

Specifications of W6811IW

• Data Interface: PCM Audio Interface
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 4.5 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• For Use With: W6811DK - KIT DEVELOPMENT FOR W6811
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6. PIN DESCRIPTION
Pin
Name
V
RO-
PAI
PAO-
PAO+
V
NC
V
FSR
PCMR
BCLKR
PUI
MCLK
BCLKT
PCMT
FST
REF
DDA
DDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
No.
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
V
DD
*
Functionality
This pin is used to bypass the on-chip 2.5V voltage reference. It needs to be
decoupled to V
external loads should be tied to this pin.
Inverting output of the receive smoothing filter. This pin can typically drive a 2
kΩ load to 1.575 volt peak referenced to the analog ground level.
This pin is the inverting input to the power amplifier. Its DC level is at the V
voltage.
Inverting power amplifier output. This pin can drive a 300 Ω load to 1.575 volt
peak referenced to the V
Non-inverting power amplifier output. This pin can drive a 300 Ω load to 1.575
Volt peak referenced to the V
Analog power supply. This pin should be decoupled to V
ceramic capacitor.
Not Connected
Digital power supply. This pin should be decoupled to V
ceramic capacitor. For correct operation, V
than V
8 kHz Frame Sync input for the PCM receive section. This pin also selects
channel 0 or channel 1 in the GCI and IDL modes. It can also be connected to
the FST pin when transmit and receive are synchronous operations.
PCM input data receive pin. The data needs to be synchronous with the FSR
and BCLKR pins.
PCM receive bit clock input pin. This pin also selects the interface mode. The
GCI mode is selected when this pin is tied to V
when this pin is tied to V
transmit and receive are synchronous operations.
Power up input signal. When this pin is tied to V
When tied to V
System master clock input. Possible input frequencies are 256 kHz, 512 kHz,
1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better
performance, it is recommended to have the MCLK signal synchronous and
aligned to the FST signal. This is a requirement in the case of 256 and 512
kHz frequencies.
PCM transmit bit clock input pin.
PCM output data transmit pin. The output data is synchronous with the FST
and BCLKT pins.
8 kHz transmit frame sync input. This pin synchronizes the transmit data
bytes.
DDA
.
SSD
SSA
, the part is powered down.
through a 0.1 μF ceramic decoupling capacitor. No
DDD
AG
voltage level.
. This pin can also be tied to the BCLKT when
- 6 -
AG
voltage level.
Publication Release Date: September, 2005
DDD
value should always be lower
SSD
DDD
. The IDL mode is selected
, the part is powered up.
SSD
SSA
with a 0.1μF
with a 0.1μF
W6811
Revision A12
AG