CY7C63813-PXC Cypress Semiconductor Corp, CY7C63813-PXC Datasheet - Page 70

• Manufacturer Part Number: CY7C63813-PXC
• Description: IC USB PERIPHERAL CTRLR 18-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Peripheral Controllerr

Specifications of CY7C63813-PXC

• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Mounting Style: Through Hole
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 40 mA
• Operating Supply Voltage: 4 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

27. DC Characteristics
28. AC Characteristics
Document 38-08035 Rev. *N
Note
V
V
V
C
I
PS/2 Interface
V
R
General Purpose IO Interface
R
V
V
V
V
V
V
V
V
V
C
Clock
T
T
T
F
F
F
F
3.3 V Regulator
V
Parameter
Parameter
IO
10. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
DI
CM
SE
OLP
ICR
ICF
HC
ILTTL
IHTTL
OL1
OL2
OL3
OH
ECLKDC
ECLK1
ECLK2
IMO1
IMO2
ILO1
ILO2
ORIP
IN
PS2
UP
LOAD
External clock duty cycle
External clock frequency
External clock frequency
Internal main oscillator frequency
Internal main oscillator frequency
Internal low power oscillator
Internal low power oscillator
Output ripple voltage
Differential input sensitivity
Differential input common mode range
Single ended receiver threshold
Transceiver capacitance
Hi-Z state data line leakage
Static output low
Internal PS/2 pull-up resistance
Pull-up resistance
Input threshold voltage low, CMOS
mode
Input threshold voltage low, CMOS
mode
Input hysteresis voltage, CMOS
Mode
Input low voltage, TTL mode
Input high voltage, TTL mode
Output low voltage, high drive
Output low voltage, high drive
Output low voltage, low drive
Output high voltage
Maximum load capacitance
[8]
[8]
[8]
Description
Description
General
[8]
(continued)
[9]
[9]
[8]
[9]
[7]
[7]
0V < V
SDATA or SCLK pins
SDATA, SCLK pins, PS/2 Enabled
Low to High edge
High to Low edge
High to low edge
I/O pin Supply = 4.0–5.5 V
I/O pin Supply = 4.0–5.5 V
I
I
I
I
External clock is the source of the
CPUCLK
External clock is not the source of the
CPUCLK
No USB present
With USB present
Normal mode
Low power mode
10 Hz to 100 MHz at CLOAD = 1 μF
OL1
OL1
OL2
OH
= 2 mA
= 50 mA
= 25 mA
= 8 mA
IN
< 3.3 V
Conditions
Conditions
–
–
–
–
–
–
V
CY7C63310, CY7C638xx
CC
0.187
23.64
29.44
35.84
40%
30%
22.8
Min
–10
Min
3%
0.2
0.8
0.8
2.0
45
–
–
3
4
–
–
–
–
0
–
–0.5
Typical
Typical
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
37.12
47.36
Max
65%
55%
10%
Max
25.2
24.3
200
2.5
0.4
0.8
0.8
0.4
0.4
20
10
12
50
55
24
24
–
2
7
–
Page 70 of 86
mV
MHz
MHz
MHz
MHz
Unit
Unit
V
V
V
kHz
kHz
KΩ
μA
pF
KΩ
pF
%
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
p-p
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