AT83C26-ALRUL Atmel, AT83C26-ALRUL Datasheet
AT83C26-ALRUL
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AT83C26-ALRUL Summary of contents
Page 1
... The AT83C26 is a smart card reader interface IC for smart card reader/writer applica- tions such as EFT/POS terminals and set top boxes. It enables the management of any type of smart card from any kind of host AT83C26 can be connected in parallel thanks to the programmable TWI address. Its high efficiency DC/DC converters and low quiescent current in stand-by mode make it particularly suited to low power and portable applications ...
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... Controller SDA I/O1 I/0 I/O2 Selection AUX1 AUX2 Clock Circuit CCLK Clock Controller CLK Note: AT83C26 2 CVSSB CVCCB CVCCINB LIB DC/DC Converter B Main Control Timer & Logic Unit 16 bits 1. CRST3/CC82 are on the same pin. CIO3/CC42 are on the same pin. If complete Smart card 2 interface is used, SAM/SIM3 isn’ ...
Page 3
... CCLK3 3 4 CVCC4 5 QFN 48 6 CRST4 TOP VIEW CCLK4 7 CIO4 8 CIO5 9 CCLK5 10 CRST5 11 CVCC5 INT 36 CLK 35 34 A2/CK A1/RST 33 AUX1 32 AUX2 31 IO1 30 IO2 29 SCL 28 SDA 27 BYPASS 26 VSS INT 35 CLK 34 A2/CK 33 A1/RST 32 AUX1 31 AUX2 30 IO1 29 IO2 SCL 28 SDA 27 26 BYPASS VSS 25 AT83C26 3 ...
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... CIO1 16 CCLK1 17 CRST1 18 CVCCIN1 19 CPRES1 20 CVCC1 21 CVCC1 AT83C26 4 Pad Type Description PWR VCC pin for SC3 interface. See SC2_CFG1 register: I/O CVCC3 If SC2_FULL bit = 0, CRST pin for SC3 interface. pull up If SC2_FULL bit = 1, CC8 pin for SC2 interface. CVCC3 O CCLK pin for SC3 interface. ...
Page 5
... Extra supply voltage (Micro controller power supply). EVCC is used to supply the internal level shifters of host interface pins. PWR EVCC is connected to the host power supply. EVCC voltage can be directly connected to VCC if the host power supply and the AT83C26 power supply is the same. AT83C26 5 ...
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... PWR DC/DCB output. Micro controller interface function: reset signal. • power on reset I/O • A low level on this pin keeps the AT83C26 under reset even if VCC open drain applied on power-on. It also resets the AT83C26 if applied when the AT83C26 is running. • Asserting RESET Card presence for SC2 interface ...
Page 7
... Input/Output with Pull-up Configuration (CIOn with and (CC4n, CC8n with Figure 2. Input/Output with Pull-up Configuration Port latch Data 7511D–SCR–02/ DCCLK CLOCK DELAY Strong PMOS N NMOS Input Data P 2 DCCLK CLOCK DELAY Strong PMOS N NMOS Input Data AT83C26 P Keep Pin P Medium Slew control with CIOn_SLEW_CTRL bits Pin ( ...
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... Input/Output with Open Drain Configuration (SDA, SCL, RESET) Figure 3. Input/Output with Open Drain Configuration Port latch Data Output Configuration (CCLKn with Figure 4. Output Configuration Port latch Data Output Configuration (CRSTn with Figure 5. Output Configuration Port latch Data AT83C26 8 N NMOS Input Data P Strong PMOS N NMOS PMOS ...
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... Figure 6. Open Drain Output with programmable pull-up Input Configuration (A1, A2, CLK, BYPASS) Figure 7. Input Input with programmable pull-up Configuration (CPRES1, CPRES2) Figure 8. Input with programmable pull-up 7511D–SCR–02/07 INT_PULLUP bit Port latch N Data NMOS Input Data INT_PULLUP bit Input Data AT83C26 P Weak Pin Pin P Weak Pin 9 ...
Page 10
... Frame Structure The structure of the TWI bus data frames is made of one or a series of write and read com- mands completed by STOP. Write commands to the AT83C26 have the structure: ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S) Read commands to the AT83C26 have the structure: ADDRESS BYTE + DATA BYTE(S) The ADDRESS BYTE is sampled on A2/CK and A1/RST after each reset (hard/soft/general call) but A2/CK, A1/RST can be used for transparent mode after the reset ...
Page 11
... Slave Address on 7 Bits Address Byte A2 A1 (A1/RST pin) Command acknowledgement from slave command and/or data stop condition R for READ Command 0 for WRITE Command Address Byte for for Read Write Command 0x43 0x42 0x47 0x46 0x4B 0x4A 0x4F 0x4E AT83C26 11 ...
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... If BYPASS pin high level, the bandgaps are switched off. Smart Card Interfaces The AT83C26 enables the management smart card interfaces. Due to shared IOs between SC2 and SC3, the user should choose between a full SC2 interface (with CC4 and CC8) or SC3 interface. ...
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... The transparent mode with A2/CK pin is available on SCn interface. The CKSn[2:0] register is used to select this transparent mode between A2/CK and CCLKn. The bit CKSTOPn must be cleared to have CCLKn running according to CKSn[2:0]. 7511D–SCR–02/07 SC2_FULL = 0 SC2 without CC4and CC8 + SC3 interface CPRES2 CRST2 CIO2 CCLK2 CRST3 CIO3 CCLK3 AT83C26 13 ...
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... If the ARTn bit is reset, CRSTn pin is driven by CARDRSTn bit. • If the ARTn bit is set, CRSTn pin is controlled and follows the “Automatic Reset Transition” (see Activation sequence page 25). • A transparent mode with A1/RST pin. Figure 5. CRSTn Block Diagram A1/RST AT83C26 14 Internal oscillators CLK DCK[2:0] CKSn[2:0] A2/CK ...
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... If IODIS1 is reset, data are bidirectional between the I/O1, I/O2, AUX1, AUX2 pins (see IO_SELECT register) and CIO1, CC41, CC81 pins. 7511D–SCR–02/07 CARDRSTn bit tb delay CARDRSTn bit IO1 IO2 HiZ Multiplex control IODIS1 bit IOSEL[3:0] AT83C26 0 CRSTn 1 ARTn bit 0 1 CARDIO1 bit 0 1 CARDC41 bit 0 1 ...
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... Transparent mode (IO signal and CIO are linked after level shifter) According to IO_SELECT register value and IODISn bits values, one of 4 input pins (IO1, IO2, AUX1 or AUX2) is linked to the selected output. The idle state is the high level. Each signal is bidirectional. AT83C26 16 IO1 IO2 ...
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... If a master switch appears before this minimum delay, the electrical conflict delay is (DCCLK period) * (CLK period) Figure 11. Electrical conflict IO CIO 7511D–SCR–02/07 IO master t2 CIO slave t1 t1 CIO pad becomes output master t2 slave t1 slave master t1 t1 slave master AT83C26 17 ...
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... An automatic mode is proposed. The VCARDn[1:0] value is used to automatically adjust the slew rate. For specific cases, like long wires between AT83C26 and smart card connector for example, the user can forced the slew rate. The rising edge and the falling edge are modified with the slew rate control for CCLKn. ...
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... Closed = 0 Open INT_PULLUP Bit INT CARDDET1 Bit = 1 No Card if CPRES1 = Card if CPRES1 = 1 FILTERING CDS1[2-0] CARDDET2 Bit = 1 No Card if CPRES2 = Card if CPRES2 = 1 FILTERING = 0 Closed CDS2[2- Open ITDIS2 Bit AT83C26 CARDIN1 bit = 1 Card Inserted = 0 No Card CARDIN2 bit = 1 Card Inserted = 0 No Card 19 ...
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... DC/DC converter is ready. Increment of DEMBOOSTA[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. So once the DC/DC converter is ready it advised to dec- rement the DEMBOOSTA[1:0] bits to restore the overflow current to its normal or desired value. AT83C26 20 7511D–SCR–02/07 ...
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... This control is done by means of bits DEM- BOOSTB[1:0], which increases progressively the startup current level. 7511D–SCR–02/07 DEMBOOSTA[1:0]=[0:0] Set Time-out VCARD_OK1=1 Time-out Expired Increment DEMBOOSTA[1:0] DEMBOOSTA[1: Maximum? DC/DC A Converter Initialization Failure END AT83C26 Decrement DEMBOOSTA[1:0] to adjust the current overflow END 21 ...
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... Increment of DEMBOOSTB[1:0] bits increases at the same time the current overflow level in the same proportion as the startup current. So once the DC/DC B converter is ready it advised to decrement the DEMBOOSTB[1:0] bits to restore the overflow current to its normal or desired value. AT83C26 22 DEMBOOSTB[1:0]=[0:0] Set Time-out VDCB_OK=1 ...
Page 23
... VCARD2[1:0]). Figure 11. LDOn Initialization Procedure ( The LDOn output voltage must before to program 1.8V/3V/5V. 7511D–SCR–02/07 Init condition: DCDCB started (VDCB_OK = 1) Start LDOn, write VCARDn[1:0] Set Timer 2ms IPLUSn = 1 VCARD_OKn = 1 Time-out Expired and IPLUSn=1 ? LDOn initialization failure AT83C26 LDOn started 23 ...
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... Wait of the end of the DC/DC (or LDO) init with a polling on VCARD_OKn bit or wait 3. CKSTOPn, IODISn are programmed by software. CKSTOPn bit is reset to have the 4. CRSTn pin is controlled by software using CARDRSTn bit. AT83C26 24 writing command in VCARDn[1:0] starts the DC/DC (or LDO). for INT to go Low. When VCARD_OKn bit is set (by hardware), CARDIOn bit should be set by software ...
Page 25
... CKSTOPn and IODISn are set (those bits are further explained in the registers description) The user should check the AT83C26 status and possibly resume the activation sequence if one TWI transfer is not acknowledged during the activation sequence. SCn_CFG0 register). This writing starts the DC/DC converter (or LDO). ...
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... ISO 7816 constraints 200 card clock cycles Timer[1-0] reset value is 400. Warm reset (n= The AT83C26 offers a simple and accurate way to control the CRSTn signal during a warm reset. After an activation sequence (cold reset), a warm reset is started with a low level on CRST dur- ing a define delay (between 40000 and 45000 clock cycles for example). ...
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... AT83C26 power supply is present. The DCCLK signal is used for deactivation sequence timings. • Emergency deactivation mode: This mode is used when the AT83C26 power supply is took off. Deactivation sequence on SCn interface (n= The card automatic deactivation is triggered when one the following condition occurs: • ...
Page 28
... Software TWI Reset (SC1, SC2, SC3, SC4, SC5) • Power fail on VCC (SC1, SC2, SC3, SC4, SC5) If the power supply is disconnected, a standard deactivation is started when VCC = VPFDP. When VCC is equal to VPFDM, the emergency deactivation occurs and eventually ends the standard deactivation. AT83C26 28 CVCC CRST CCLK CIO, ...
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... TWI address at reset. If A2/CK input is tied to the host micro controller and its reset value is unknown, a general call on the TWI bus allows to reset all the AT83C26 devices and set its address after A2/CK input is fixed. 7511D–SCR–02/07 ...
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... A1/RST CRST CIO I/O1 CC4 AUX1 AUX2 CC8 AT83C26 A2/CK CCLK CIO I/O2 INSERT1 or INSERT2 bits set (card insertion/extraction or bit set by software) VCARD_INTn (n=1,2,3,4,5) bits set (the DC/ LDO2 to LDO5 output voltage has settled) VDCB_INT bit set (the DC/DC B output voltage has settled) ...
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... Several AT83C26 devices can share the same interrupt pin and the micro controller can identify the interrupt sources by polling the interrupt bits of the AT83C26 devices using TWI commands. A TWI read command of the interrupt bit corresponding to the IT clears the bit. When all IT bits are cleared, the INT output becomes high ...
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... The status for the ATRERRn ( controlled by reading of values in CAPTURE_MSB and CAPTURE_LSB. Slew rate control The AT83C26 proposed a slew rate control on CIOn and CCLKn pins (n= 5). The con- trol operates on rising and falling edges of CCLKn and only on rising edge of CIOn. Four modes are available: • ...
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... Configuration of parameters for smart card interfaces. 7. Write SC2 interface: SC2_CFG0, SC2_CFG1, SC2_CFG2 Configuration of smart card interface 2. 8. Write SC3 interface: SC3_CFG0, SC3_CFG2 Configuration of SIM/SAM interface 3. 9. Write SC4 interface: SC4_CFG0, SC4_CFG2 Configuration of SIM/SAM interface 4. 7511D–SCR–02/ SC1_CFG0 on 6 Bits AT83C26 ...
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... XX10 8. Write SC3 interface 0100 XX10 9. Write SC4 interface 0100 XX10 10. Write SC5 interface 0100 XX10 11. Write DCDCB config 0100 XX10 12. Write SLEW_CTRL config 0100 XX10 AT83C26 34 Command Byte Data Byte 1 [0] [1] 0000 0110 1111 1111 (10 + SC1_CFG0 6 bits) SC1_CFG1 1111 1100 ...
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... AT83C26 After 6. After 7. After write write write command command command number 10 number 11 number 12 SC5_CFG0 DCDCB SLEW_CTRL_1 SC5_CFG2 ...
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... Registers summary The table below gives a quick view on AT83C26 registers. Table 8. Smart card 1 interface registers 7 SC1_CFG0 1 SC1_CFG1 X SC1_CFG2 0 SC1_CFG3 X SC1_CFG4 X SC1_INTERFACE 0 SC1_STATUS CC81 Table 9. Smart card 2 interface registers 7 SC2_CFG0 VCARD_INT2 SC2_CFG1 X SC2_CFG2 ART2 Table 10. SIM/SAM 3 interface registers 7 SC3_CFG0 VCARD_INT3 SC3_CFG2 ART3 Table 11 ...
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... CC42 CRST2 ITDIS5 ITDIS4 ITDIS3 ICCADJB STEPREGB VDCB1 CCLK1_SLEW_CT CCLK1_SLEW_CT CIO1_SLEW_CT RL1 RL0 RL1 CCLK3_SLEW_CT CCLK3_SLEW_CT CIO3_SLEW_CT RL1 RL0 RL1 CCLK5_SLEW_CT CCLK5_SLEW_CT CIO5_SLEW_CT RL1 RL0 RL1 AT83C26 0 Bit 8 Bit 0 Bit 8 Bit 0 IOSEL0 0 DEMBOOSTB0 CIO2 ITDIS2 0 VDCB0 1 0 CIO1_SLEW_CTR L0 CIO3_SLEW_CTR L0 CIO5_SLEW_CTR L0 37 ...
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... VCARD1[1:0] Reset value = 0x 1000 0000 Table 18. SC1_CFG1 (Config Byte 1 for SC1 ART1 SHUTDOWNA AT83C26 INSERT1 ICARDERR1 Description These bits cannot be programmed and are read as 1-0. Answer to Reset Interrupt for SC1 This bit is set when the card clock counter overflows (no falling edge on CIO1 is received before the overflow of the card clock counter) ...
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... CDS1[2- 256 identical samples Note: 1. When CDS[2- card insertion (even if CLK is stopped) puts a low level on INT pin. This can be used to wake up the external micro controller and restart CLK when a card is inserted in the AT83C24 DCK1 DCK0 (typically a 1 MΩ resistor CKS12 CKS11 AT83C26 0 CKS10 39 ...
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... X Bit Number Bit Mnemonic 7-5 X AT83C26 40 1. When CKS1 value is changed a special logic insures no glitch occurs on the CCLK1 pin and actual configuration changes can be delayed by half a period to two periods of CCLK1. 2. CCLK1 must be stopped with CKSTOP1 bit before switching from CKS1 = ( CKS1 = ( vice versa. ...
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... X 7511D–SCR–02/07 Description CI overflow adjust CC This bit controls the DC/DCA sensitivity to any overflow current. Set this bit to decrease the DC/DCA sensitivity (CI Clear this bit to have a normal configuration. The reset value STEPREGA INT_PULLUP Description AT83C26 is increased by about 20%). CC_ovf CRST_SEL1 0 41 ...
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... CRST_SEL1 Reset value = 0x X000 0000 Table 22. SC1_INTERFACE (Interface Byte for SC1 IODIS1 CKSTOP1 AT83C26 42 Description DC/DC A Maximum Startup Current drawn from power supply 00: Normal average 01: Normal + 18% 10: Normal + 18% (and boost on oscillator) 11: Normal + 40% Step Regulator mode Clear this bit to enable the automatic step-up converter (CVCC is stable even if VCC is not higher than CVCC) ...
Page 43
... Set this bit to drive the CIO1 pin High with the on-chip pull-up (according to IODIS1 bit value). The pin can then be an input (read in SC1_STATUS register). Clear this bit to drive a low level on the CIO1 pin (according to IODIS1 bit value CARDIN1 VCARD_OK1 Description Card CC8 This bit provides the actual level on the CC8 pin when read VCARD_INT1 CRST1 AT83C26 0 CIO1 43 ...
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... Table 24. SC2_CFG0 () VCARD_INT VCARD_OK 2 2 ATRERR2 AT83C26 44 Description Card CC4 This bit provides the actual level on the CC4 pin when read. Card Presence Status This bit is set when a card is detected cleared otherwise. SC1 Voltage Status This bit is set by the DCDCA when the output voltage remains within the voltage range specified by VCARD1[1:0] bits ...
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... VCRD2[1:0] = 10: 3V class B VCRD2[1:0] = 11: 5V class A No card deactivation is performed when the voltage is changed. The micro controller should deactivate the card before changing the voltage and activating the card again. The reset value is 00. AT83C26 goes out of the voltage range specified by VCRDN field ...
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... CDS2[2- identical samples 2-0 CDS2[2:0] CDS2[2- identical samples CDS2[2- identical samples CDS2[2- 128 identical samples CDS2[2- 256 identical samples Note: Reset value = 0x XX10 1010 AT83C26 CARDDET2 PULLUP2 CIO3/CC42 is CC42 and CRST3/CC82 is CC82. Interface 3 LDO is disabled. CARDCK3 is reset and CKSTOP3 to stop CCLK on SC3. ...
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... CKS2 [3: CCLK2 = CLK / 4 1. When CKS2 value is changed a special logic insures no glitch occurs on the CCLK2 pin and actual configuration changes can be delayed by half a period to two periods of CCLK2. 2. CCLK2 must be stopped with CKSTOP2 bit before switching from CKS2 = ( CKS2 = ( vice versa CKS22 CKS21 AT83C26 0 CKS20 47 ...
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... VCARD_OK3 5 ATRERR3 VCARDERR3 1-0 VCARD3[1:0] Reset value = 0x 000X 0000 AT83C26 ATRERR3 X X Description SC3 voltage interrupt This bit is set when VCARD_OK3 bit is set. This bit is cleared when read by the micro controller. SC3 Voltage Status This bit is set by the LDO3 when the output voltage remains within the voltage range specified by VCARD3[1:0] bits ...
Page 49
... When CKS3 value is changed a special logic insures no glitch occurs on the CCLK3 pin and actual configuration changes can be delayed by half a period to two periods of CCLK3. 2. CCLK3 must be stopped with CKSTOP3 bit before switching from CKS3 = ( CKS3 = ( vice versa CKSTOP3 CK32 CKS31 AT83C26 0 CKS30 49 ...
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... VCARD_OK4 5 ATRERR4 VCARDERR4 1-0 VCARD4[1:0] Reset value = 0x 000X X000 AT83C26 Description SC4 voltage interrupt This bit is set when VCARD_OK4 bit is set. This bit is cleared when read by the micro controller. SC4 Voltage Status This bit is set by the LD04 when the output voltage remains within the voltage range specified by VCARD4[1:0] bits ...
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... When CKS4 value is changed a special logic insures no glitch occurs on the CCLK4 pin and actual configuration changes can be delayed by half a period to two periods of CCLK4. 2. CCLK4 must be stopped with CKSTOP4 bit before switching from CKS4 = ( CKS4 = ( vice versa CKSTOP4 CKS42 CKS41 AT83C26 0 CKS40 51 ...
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... VCARD_OK5 5 ATRERR5 VCARDERR5 1-0 VCARD5[1:0] Reset value = 0x 000X X000 AT83C26 ATRERR5 X X Description SC5 voltage interrupt This bit is set when VCARD_OK5 bit is set. This bit is cleared when read by the micro controller. SC5 Voltage Status This bit is set by the LDO5 when the output voltage remains within the voltage range specified by VCARD5[1:0] bits ...
Page 53
... When CKS5 value is changed a special logic insures no glitch occurs on the CCLK5 pin and actual configuration changes can be delayed by half a period to two periods of CCLK5. 2. CCLK5 must be stopped with CKSTOP5 bit before switching from CKS5 = ( CKS5 = ( vice versa CKSTOP5 CKS52 CKS51 AT83C26 0 CKS50 53 ...
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... Reset value = 0x 0000 0000 Table 36. CAPTURE_LSB (Capture LSB for SC1, SC2, SC3, SC4, SC5 bit 7 bit 6 Bit Number Bit Mnemonic Description See Section “Software activation for SCn (n= interfaces and ARTn bit = 1”, page bits Reset value = 0x 0000 0000 AT83C26 Bit 13 Bit 12 Bit Bit 5 Bit 4 ...
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... CIO2 - (1) CIO3 - (1) CIO4 - (1) CIO5 - CIO1 CIO2 CIO1 CIO2 CIO1 CIO2 CIO1 CIO2 CIO1 CIO3 CIO1 CIO4 CIO1 CIO5 CIO1 CIO5 CIO2 CIO5 CIO2 CIO4 CIO2 CIO5 AT83C26 2 1 IOSEL2 IOSEL1 IOSEL0 AUX1 AUX2 (1) ( (1) ( (1) ( (1) ( (1) ( CC41 CIO3/CC42 CC41 CIO4 CC41 CIO5 ...
Page 56
... Note: AT83C26 input (IO1, IO2, AUX1, AUX2) is selected for a SCIB pin (CIOn, CC4n CC8n), and if the smart card interface is started, the electrical level on the SCIB pin corresponds to the CAR- DIOn, CARDC4n or CARDC8n bit value. 2. For IOSEL[3:0] = 0xOE and IOSEL[3:0] = 0x0F, the CARDRST3 bit must be set to connect AUX2 to CRST3/CC82 pin. 7511D– ...
Page 57
... The pin can then be an input (read in STATUSB register). Clear this bit to drive a low level on the CIO2 pin when isolated from the host. Configuration for DC/DCB startup current. 00: Normal average 01: Normal + 18% 10: Normal + 18% (and boost on oscillator) 11: Normal + 40% AT83C26 2 1 DEMBOOSTB1 DEMBOOSTB0 0 57 ...
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... CARDIN2 5 CIO5 4 CIO4 3 CRST3/CC82 2 CIO3/CC42 1 CRST2 0 CIO2 Reset value = reset value depends on hardware configuration AT83C26 CRST3/ CIO5 CIO4 CC82 Description Card Presence Status 2 This bit is set when a card is detected cleared otherwise. Card CIO5 This bit provides the actual level on the CIO5 pin when read. ...
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... Set this bit to disable interrupts from the interface 3 (the flags are set but INT pin is not driven). Clear this bit to allow interrupts. Interrupt Disable of Smart Card Interface 2 Set this bit to disable interrupts from the interface 2(the flags are set but INT pin is not driven). Clear this bit to allow interrupts. AT83C26 2 1 ITDIS4 ITDIS3 ...
Page 60
... VDCB_INT 5 VDCB_OK ICCADJB 2 STEPREGB 1-0 VDCB[1:0] Reset value = 0x 0000 0000 AT83C26 VDCB_OK 0 ICCADJB Description Shutdown DCDCB Set this bit to reduce the power consumption. An automatic de-activation sequence will be done. Clear this bit to enable VDCB. The reset value is 0. DC/DC B voltage interrupt This bit is set when VCARD_OKB bit is set. ...
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... If set, this bit increases the startup and overflow current of LDO4 (+60%) If set, this bit increases the startup and overflow current of LDO3 (+60%) If set, this bit increases the startup and overflow current of LDO2 (+60%) Do not clear this bit. Do not clear this bit. Do not clear this bit. Do not clear this bit. AT83C26 ...
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... CIO2_SLEW_CT RL1 RL0 Bit Number Bit Mnemonic 7-6 CCLK2_SLEW_CTRL[1-0] 5-4 CIO2_SLEW_CTRL[1-0] 3-2 CCLK1_SLEW_CTRL[1-0] 1-0 CIO1_SLEW_CTRL[1-0] Reset value = 0x 1111 1111 AT83C26 CIO2_SLEW_CT CCLK1_SLEW_CT RL1 RL0 RL1 Description 0 0: Mode 1 (optimum for CVCC2=5V Mode 2 (optimum for CVCC2=3V Mode 3 (optimum for CVCC2=1.8V Automatic mode The reset value is 11 ...
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... Mode 1 (optimum for CVCC3=5V Mode 2 (optimum for CVCC3=3V Mode 3 (optimum for CVCC3=1.8V Automatic mode The reset value is 11 Mode 1 (optimum for CVCC3=5V Mode 2 (optimum for CVCC3=3V Mode 3 (optimum for CVCC3=1.8V Automatic mode The reset value is 11. AT83C26 2 1 CCLK3_SLEW_CTRL CIO3_SLEW_CT CIO3_SLEW_CTR 0 RL1 0 L0 ...
Page 64
... Table 46. SLEW_CTRL_3 (Slew control for SC5 Bit Number Bit Mnemonic 7-4 X 3-2 CCLK5_SLEW_CTRL[1-0] 1-0 CIO5_SLEW_CTRL[1-0] Reset value = 0x XXXX 1111 AT83C26 CCLK5_SLEW_CTR Description 0 0: Mode 1 (optimum for CVCC5=5V Mode 2 (optimum for CVCC5=3V Mode 3 (optimum for CVCC5=1.8V Automatic mode The reset value is 11. ...
Page 65
... Typ Max Unit 2.59 2.75 V 2.40 2.56 V 190 300 mV 10s µs 10s DCDCA, DCDCB and LDOs on mA +12 with load VCC = 5.5V SHUTDOWNA bit = 1 SHUTDOWNB bit = µA VCC = 5.5V 48 MHz AT83C26 Test Conditions 65 ...
Page 66
... Vcardok high level threshold Vcardok down Vcardok low level threshold T CVCC valid to 0.4V VHL T CVCC 0 to valid VLH Table 51. Smart Card 1 Class B, 3V (CVCC1) Symbol Parameter CVCC Smart card voltage AT83C26 66 Min Typ 2.2 VCC - 0.7V Min Typ 2.2 Min Typ Max 4 ...
Page 67
... Min Typ Max 1.656 1.8 1.944 30 38 0.05 1.8 1.718 30 80 400 220 2000 Min Typ 4 4.646 150 AT83C26 Unit Test Conditions mA With low ESR capacitance mV (0.1 Ohms max =10µF µ 10µF µs L Unit Test Conditions V Load = 35mA ...
Page 68
... CVCC valid to 0.4V VHL T CVCC 0 to valid VLH Table 56. Smart Card Class A, 5V (CVCC3, CVCC4, CVCC5) Symbol Parameter CVCC Smart card voltage Card Supply Current Overflow: CI _ovf CC ICCADJB = 0 (reset value) AT83C26 68 Min Typ Max 200 2000 Min Typ Max 2. ...
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... Min Typ Max 2. 175 3 2.791 40 500 100 2000 Min Typ Max 1.656 1.8 1.944 178 1.8 1.65 30 500 100 2000 AT83C26 Unit Test Conditions =470nF µ 470nF µs L Unit Test Conditions V Load = 30mA =470nF µs L µ 470nF L Unit ...
Page 70
... IH I Output Short Circuit Current OS Low level voltage stability (taking into account PCB design) High level voltage stability (taking into account PCB design) Rise time t R (see Tables 63 to 65) AT83C26 70 Min Typ Max 0.3 0.8 CVCC 16 16 -0.25 0.6 -0.25 0.4 -0 ...
Page 71
... Min Typ Max AT83C26 Unit Test Conditions C = 30pF Class 30pF Class 30pF Class C L Unit Test Conditions Short to VSS µA PULLUP1 = 1: Internal pull-up active Short to VSS µA PULLUP2 = 1: ...
Page 72
... CCLKn_SLEW_CTRL[1-0] = 11(mode auto) Rise time/ Fall time t R/F with CCLKn_SLEW_CTRL[1- (1.8V) Table 68. Slew rate on CCLKn with CVCCn= 1.8V (n= 5), Mode 3 Symbol Parameter Rise time/ Fall time t with CCLKn_SLEW_CTRL[1- (1.8V CCLKn_SLEW_CTRL[1-0] = 11(mode auto) AT83C26 72 Min Typ Max 30 12 Min Typ Max 25 Min Typ Max ...
Page 73
... CIO2, CC42, CC82 Card 2 CPRES2 CCLK2 10µH 100nF 10µF V VSS CC VSS VSS V CC 4.7µH 100nF VSS VSS CVCC1 CVCC1IN 10µF 100nF CVSS AT83C24 DVCC 100nF CRST VSS CIO, CC4, CC8 Card 0 CPRES CCLK AT83C26 10µF VSS 2.2µF VSS CVSS 73 ...
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... Ordering Information Part Number AT83C26-PLTUL AT83C26-PLRUL AT83C26-RKTUL AT83C26-RKRUL Samples Part Number AT83C26-PLTEL AT83C26-RKTEL AT83C26 74 Supply Voltage Temperature Range 3V to 5.5V Industrial green 3V to 5.5V Industrial green 3V to 5.5V Industrial green 3V to 5.5V Industrial green Supply Voltage Temperature Range 3V to 5.5V 25° 5.5V 25° ...
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... Package Drawings VQFP48 7511D–SCR–02/07 AT83C26 75 ...
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... QFN48 AT83C26 76 7511D–SCR–02/07 ...
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... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’sAtmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © ...