LTC4263CS#TRPBF Linear Technology, LTC4263CS#TRPBF Datasheet - Page 8

• Manufacturer Part Number: LTC4263CS#TRPBF
• Description: IC IEEE 803.2AF CNTRLR 14-SOIC
• Manufacturer: Linear Technology
• Type: Power Over Ethernet (PoE)r

Specifications of LTC4263CS#TRPBF

• Applications: Power Interface Switch for Power Over Ethernet (PoE) Devices
• Voltage - Supply: 48V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Current - Supply: 1mA
• Interface: IEEE 802.3af
• Controller Type: Power Sourcing Equipment Controller (PSE)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN FUNCTIONS
LTC4263
LED (Pin 1): Port State LED Drive. This pin is an open drain
output that pulls down when the port is powered. Under port
fault conditions, the LED will fl ash in patterns to indicate
the nature of the port fault. See the Applications Informa-
tion section for a description of these patterns. When the
LTC4263 is operated from a single 48V supply, this pin is
pulsed low with a 6% duty cycle during the periods when
the LED should be on. This allows use of a simple inductor,
diode, and resistor circuit to avoid excess heating due to
the large voltage drop from V
Information section for details on this circuit.
LEGACY (Pin 2): Legacy Detect. This pin controls whether
legacy detect is enabled. If held at V
enabled and testing for a large capacitor is performed to
detect the presence of a legacy PD on the port. See the
Applications Information section for descriptions of legacy
PDs that can be detected. If held at V
compliant PDs are detected. If left fl oating, the LTC4263
enters force-power-on mode and any PD that generates
between 1V and 10V when biased with 270μA of detection
current will be powered as a legacy device. This mode is
useful if the system uses a differential detection scheme
to detect legacy devices. Warning: Legacy modes are not
IEEE 802.3af compliant.
MIDSPAN (Pin 3): Midspan Enable. If this pin is connected
to V
delay occurs after every failed detect cycle unless the
result is open circuit. If held at V
failed detect cycles.
PWRMGT (Pin 4): Power Management. The LTC4263
sources current at the PWRMGT pin proportional to the
class of the PD that it is powering. The voltage of this pin
is checked before powering the port. The port will not
turn on if this pin is more than 1V above V
PWRMGT pins of multiple LTC4263s together with a resistor
and capacitor to V
power management is not used, tie this pin to V
V
be tied together on the PCB.
8
SS
(Pins 5, 6): Negative 48V Supply. Pins 5 and 6 should
DD5
, Midspan backoff is enabled and a 3.2 second
SS
to implement power management. If
(DFN/SO)
DD48
SS
. See the Applications
, no delay occurs after
SS
DD5
, only IEEE 802.3af
, legacy detect is
SS
. Connect the
SS
.
OSC (Pin 7) Oscillator for AC Disconnect. If AC discon-
nect is used, connect a 0.1μF X7R capacitor from OSC to
V
DC disconnect.
ACOUT (Pin 8): AC Disconnect Sense. Senses the port
to determine whether a PD is still connected when in AC
disconnect mode. If port capacitance drops below about
0.15μF for longer than T
AC disconnect is used, connect this pin to the port with
a series combination of a 1k resistor and a 0.47μF 100V
X7R capacitor. See the Applications Information section
for more information.
OUT (Pins 9, 10): Port Output. If DC disconnect is used,
these pins are connected to the port. If AC disconnect
is used, these pins are connected to the port through a
parallel combination of a 1A diode and a 500k resistor.
Pins 9 and 10 should be tied together on the PCB. See the
Applications Information section for more information.
V
0.1μF capacitor to V
SD (Pin 12): Shutdown. If held low, the LTC4263 is pre-
vented from performing detection or powering the port.
Pulling SD low will turn off the port if it is powered. When
released, a 4-second delay will occur before detection is
attempted.
ENFCLS (Pin 13): Enforce Class Current Limits. If held
at V
class 1 or class 2 PDs. If ENFCLS is held at V
remains at 375mA (typ) for all classes.
V
to V
bypass capacitor to V
When the internal regulator is used, this pin should only
be connected to the bypass capacitor and to any logic pins
of the LTC4263 that are being held at V
Exposed Pad (Pin 15, DE Package Only): V
connected to V
heatsink for the internal MOSFET.
SS
DD48
DD5
. Tie OSC to V
DD5
SS
(Pin 14): Logic Power Supply. Apply 5V referenced
, if such a supply is available, or place a 0.1μF
(Pin 11): 48V Return. Must be bypassed with a
, the LTC4263 will reduce the I
SS
SS
on the PCB. The Exposed Pad acts as a
SS
to disable AC disconnect and enable
SS
.
to enable the internal regulator.
MPDO
the port is turned off. If
DD5
CUT
.
threshold for
SS
. Must be
SS
, I
4263fe
CUT