LTC4259ACGW Linear Technology, LTC4259ACGW Datasheet
LTC4259ACGW
Specifications of LTC4259ACGW
Available stocks
Related parts for LTC4259ACGW
LTC4259ACGW Summary of contents
Page 1
... IEEE 802.3af Compliant Endpoint and Midspan Power Sources ■ IP Phone Systems ■ DTE Power Distribution , LTC and LT are registered trademarks of Linear Technology Corporation. HotSwap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. U TYPICAL APPLICATIO INT ...
Page 2
... Open Circuit, Measured at DETECT n Pin 0mA < I < 31mA CLASS Into Short (V = 0V) DETECT U W ORDER PART TOP VIEW 1 36 OSCIN NUMBER BYP 2 35 AUTO 3 OUT1 INT 34 LTC4259ACGW 4 GATE1 SCL SENSE1 6 31 OUT2 AD3 7 30 GATE2 AD2 8 29 SENSE2 9 V AD1 28 EE ...
Page 3
ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T (Note 6). SYMBOL PARAMETER I Classification Threshold Current TCLASS Gate Driver I GATE Pin Current GON I GATE Pin Current GOFF I GATE Pin Short-Circuit Pull-Down GPD ∆V External Gate Voltage ...
Page 4
LTC4259A ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T (Note 6). SYMBOL PARAMETER t Maximum Current Limit Duration During START Port Start-Up t Maximum Current Limit Duration After ICUT Port Start-Up DC Maximum Current Limit Duty Cycle CLMAX t ...
Page 5
W U TYPICAL PERFOR A CE CHARACTERISTICS Power On Sequence in Auto Mode PORT 3. –48V EE GND PORT DETECTION DETECTION VOLTAGE PHASE 1 PHASE 2 10V/DIV CLASSIFICATION V EE 50ms/DIV Current Limit Foldback ...
Page 6
LTC4259A W U TEST PORT GATE n INT Figure 2. Detect, Class and Turn-On Timing in Auto or Semiauto Modes V SENSE n V SENSE n V MIN INT ...
Page 7
DIAGRA S SCL SDA AD3 AD2 AD1 AD0 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA AD3 AD2 AD1 AD0 R/W ACK START BY ...
Page 8
LTC4259A CTIO S RESET (Pin 1): Chip Reset, Active Low. When the RESET pin is low, the LTC4259A is held inactive with all ports off and all internal registers reset to their power-up states. When ...
Page 9
CTIO S AGND (Pin 21): Analog Ground. AGND should be con- nected to the return from the – 48V supply. AGND and DGND should be tied together. SENSE4 (Pin 22): Port 4 Current Sense Input. ...
Page 10
LTC4259A W TABLE 1. REGISTER AP 10 4259afb ...
Page 11
U U REGISTER FU CTIO S Interrupt Registers Interrupt (Address 00h): Interrupt Register, Read Only. A transition to logical 1 of any bit in this register will assert the INT pin (Pin 3) if the corresponding bit in the Int ...
Page 12
LTC4259A U U REGISTER FU CTIO S disconnect enabled independently of the state of the Osc Fail bit. See AC Disconnect under Applications Information for more details. Bit 4 indicates that V low the V UVLO level (typically –28V). Bit ...
Page 13
U U REGISTER FU CTIO S Detect/Class Enable (Address 14h): Detection and Clas- sification Enable, Read/Write. The lower four bits of this reg- ister enable the detection circuitry at the corresponding port if that port is in Auto or Semiauto ...
Page 14
LTC4259A U U REGISTER FU CTIO S way, the condition causing the LTC4259A to pull the INT pin down must be removed before the LTC4259A will be able to pull INT down again. This can be done by reading and ...
Page 15
U U APPLICATIO S I FOR ATIO The LTC4259A provides a complete solution for detection and powering of PD devices in an IEEE 802.3af compliant system. The LTC4259A consists of four independent ports, each with the ability to detect, classify, ...
Page 16
LTC4259A U U APPLICATIO S I FOR ATIO The LTC4259A checks for the signature resistance by forcing two test currents on the port (via the DETECT n pins) in sequence and measuring the resulting voltages. It then subtracts the two ...
Page 17
U U APPLICATIO S I FOR ATIO measures the port voltage through the DETECT n pin. Note that class 4 is presently specified by the IEEE as reserved for future use. Figure 14 shows a PD load line, starting with ...
Page 18
LTC4259A U U APPLICATIO S I FOR ATIO Dual-Level Current Limit permitted to draw up to 15.4W continuously and up to 400mA for 50ms. The LTC4259A has two correspond- ing current limit thresholds, I (375mA typ) and ...
Page 19
U U APPLICATIO S I FOR ATIO Foldback Foldback is designed to limit power dissipation in the MOSFET during power-up and momentary short-circuit conditions. At low port output voltages, the voltage across the MOSFET is high, and power dissipation will ...
Page 20
LTC4259A U U APPLICATIO S I FOR ATIO noncompliant PD with only a few ohms of resistance. With foldback, the MOSFET sees a maximum of 18W for the duration START The LTC4259A’s duty cycle protection enforces 15 ...
Page 21
U U APPLICATIO S I FOR ATIO the minimum specified current. The disconnect timer counts up whenever port current is below 7.5mA (typ). If the t timer runs out, the corresponding port will be DIS turned off and the disconnect ...
Page 22
LTC4259A U U APPLICATIO S I FOR ATIO values and C is discouraged. Contact the DET DET PSE LTC Applications department for additional support. When choosing C and C , carefully consider voltage DET PSE derating ...
Page 23
U U APPLICATIO S I FOR ATIO OSCIN Input and Oscillator Requirements AC disconnect depends on an external oscillator source applied to the OSCIN pin. The LTC4259A measures port impedance by applying an amplified version of the OSCIN signal to ...
Page 24
LTC4259A U U APPLICATIO S I FOR ATIO lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. If ...
Page 25
U U APPLICATIO S I FOR ATIO V CPU DD SCL SDA TO CONTROLLER SMBALERT GND CPU U1: FAIRCHILD NC7WZ17 U2, U3: AGILENT HCPL-063L W U 0.1µF U2 200Ω U1 200Ω HCPL-063L U3 200Ω 200Ω 0.1µF HCPL-063L ISOLATED 3.3V + ...
Page 26
LTC4259A U U APPLICATIO S I FOR ATIO clock pulse. The slave must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. When the ...
Page 27
U U APPLICATIO S I FOR ATIO System Software Strategy Control of the LTC4259A hinges on one decision, the LTC4259A’s operating mode. The three choices are de- scribed under Operating Modes. In Auto mode the LTC4259A can operate autonomously without ...
Page 28
... PSE. Each paragraph below addresses a com- ponent which is critical for PSE compliance as well as possible pitfalls that can cause a PSE to be noncompliant. For further assistance please contact Linear Technology’s Applications department. Sense Resistors The LTC4259A is designed to use a 0.5Ω sense resistor monitor the current through each port ...
Page 29
U U APPLICATIO S I FOR ATIO a current loop can form. In such a loop, common mode current flows in one port and out the other, and the choke will not prevent this because the sum of the currents ...
Page 30
LTC4259A U U APPLICATIO S I FOR ATIO cases the port voltage must always stay between –44V and –57V. In addition, the 802.3af specification places specific ripple, noise and load regulation requirements on the PSE. Among other things, disturbances on ...
Page 31
... MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights Package 36-Lead Plastic SSOP (Wide .300 Inch) (Reference LTC DWG # 05-08-1642) 1.143 ± ...
Page 32
... SMAJ58A D AC S1B CONNECTOR 1/2 PULSE H2009 0.01µF 0.01µF 200V 200V 75Ω 75Ω T1 1:1 0.01µF 0.01µF 200V 200V 75Ω 75Ω T1 1000pF 1:1 2000V LT 1205 REV B • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2004 L1 RJ45 4258 F22A 4259afb ...