VNC2-64Q1B-REEL FTDI, Future Technology Devices International Ltd, VNC2-64Q1B-REEL Datasheet - Page 88

• Manufacturer Part Number: VNC2-64Q1B-REEL
• Description: IC USB HOST CTLR VINCULUM 64QFN
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculum-IIr

Specifications of VNC2-64Q1B-REEL

• Mfg Application Notes: Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote
• Controller Type: USB 2.0 Controller
• Interface: SPI Serial, USB, UART
• Voltage - Supply: 1.62 V ~ 1.98 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1046-2; VNC2-64Q1A-REEL

Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
1.2
Version -
143
Clearance No.: FTDI#
List of Figures
Figure 2-1 Simplified VNC2 Block Diagram ....................................................................................... 5
Figure 3-1 32 Pin LQFP – Top Down View ........................................................................................ 9
Figure 3-2 32 Pin QFN – Top Down View ....................................................................................... 10
Figure 3-3 48 Pin LQFP – Top Down View ...................................................................................... 11
Figure 3-4 48 Pin QFN – Top Down View ........................................................................................ 12
Figure 3-5 64 Pin LQFP – Top Down View ...................................................................................... 13
Figure 3-6 64 Pin QFN – Top Down View ........................................................................................ 14
Figure 3-7 Schematic symbol 32 Pin .............................................................................................. 15
Figure 3-8 Schematic symbol 48 Pin .............................................................................................. 16
Figure 3-9 Schematic symbol 64 Pin .............................................................................................. 17
Figure 5-1 IOBUS to Group Relationship-64 Pin .............................................................................. 27
Figure 5-2 IOBUS to UART, SPI slave0 and SPI master example ....................................................... 28
Figure 5-3 IOBUS to UART, SPI slave0 and SPI master second example ............................................ 29
Figure 5-4 IOBUS to UART, SPI slave0 and SPI master third example ................................................ 30
Figure 5-5 IOMux Utility screenshot .............................................................................................. 32
Figure 5-6 UART Example 64 pin .................................................................................................. 37
Figure 6-1 UART Receive Waveform .............................................................................................. 38
Figure 6-2 UART Transmit Waveform ............................................................................................ 38
Figure 6-3 - SPI CPOL CPHA Function ............................................................................................ 42
Figure 6-4 SPI Slave block diagram ............................................................................................... 43
Figure 6-5 Full Duplex Data Master Write ....................................................................................... 44
Figure 6-6 Full Duplex Data Master Read ....................................................................................... 45
Figure 6-7 SPI Command and Status Structure ............................................................................... 45
Figure 6-8 Half Duplex Data Master Write ...................................................................................... 46
Figure 6-9 Half Duplex Data Master Read ....................................................................................... 46
Figure 6-10 Half Duplex 3-pin Data Master Write ............................................................................ 47
Figure 6-11 Half Duplex 3-pin Data Master Read............................................................................. 47
Figure 6-12 Unmanaged Mode Transfer Diagram ............................................................................ 48
Figure 6-13 VNC1L Mode Data Write ............................................................................................. 49
Figure 6-14 VNC1L Mode Data Read .............................................................................................. 49
Figure 6-15 VNC1L Compatible SPI Command and Status Structure .................................................. 49
Figure 6-16 SPI Slave Mode Timing ............................................................................................... 52
Figure 6-17 SPI Master Data Read (VNC2 Slave Mode) .................................................................... 53
Figure 6-18 SPI Slave Mode Data Write ......................................................................................... 54
Figure 6-19 SPI Slave Mode Status Read ....................................................................................... 54
Figure 6-20 SPI Master block diagram ........................................................................................... 55
Figure 6-21 Typical SPI Master Timing ........................................................................................... 57
Figure 6-22 Asynchronous FIFO mode Read / Write Cycle ................................................................ 63
Figure 6-23 Synchronous FIFO mode Read / Write Cycle ................................................................. 65
Figure 6-24 PWM – Timing Diagram .............................................................................................. 66
Figure 6-25 GPIO Port Groups ...................................................................................................... 67
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