MAX3421EEHJ+T Maxim Integrated Products, MAX3421EEHJ+T Datasheet - Page 2

• Manufacturer Part Number: MAX3421EEHJ+T
• Description: IC USB PERIPH/HOST CNTRL 32TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3421EEHJ+T

• Controller Type: USB Peripheral Controller
• Interface: USB/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• For Use With: MAX3421EVKIT-1+ - EVAL KIT FOR MAX3421E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

♦ Eleven Registers (R21–R31) are Added to the
♦ Host Controller Operates at Full Speed or Low
♦ FIFOS
♦ Handles DATA0/DATA1 Toggle Generation and
♦ Performs Error Checking for All Transfers
♦ Automatically Generates SOF (Full-Speed)/EOP
♦ Automatically Synchronizes Host Transfers with
♦ Reports Results of Host Requests
♦ Supports USB Hubs
♦ Supports ISOCHRONOUS Transfers
♦ Simple Programming
USB Peripheral/Host Controller
with SPI Interface
2
MAX3420E Register Set to Control Host Operation
Speed
Checking
(Low-Speed) at 1ms Intervals
Beginning of Frame (SOF/EOP)
_______________________________________________________________________________________
SIE Automatically Generates Periodic SOF
(Full-Speed) or EOP (Low-Speed) Frame
Markers
SPI Master Loads Data, Sets Function Address,
Endpoint, and Transfer Type, and Initiates the
Transfer
MAX3421E Responds with an Interrupt and
Result Code Indicating Peripheral Response
Transfer Request Can be Loaded Any Time
SIE Synchronizes with Frame Markers
For Multipacket Transfers, the SIE
Automatically Maintains and Checks the
Data Toggles
SNDFIFO: Send FIFO, Double-Buffered 64-Byte
RCVFIFO: Receive FIFO, Double-Buffered 64-Byte
Features in Host Operation
♦ Built-In Endpoint FIFOS
♦ Double-Buffered Data Endpoints Increase
♦ SETUP Data Has its Own 8-Byte FIFO, Simplifying
Figure 1. The MAX3421E Connects to Any Microprocessor
Using 3 or 4 Interface Pins
The MAX3421E connects to any microprocessor (µP)
using 3 or 4 interface pins (Figure 1). On a simple
microprocessor without SPI hardware, these can be
bit-banged general-purpose I/O pins. Eight GPIN and
eight GPOUT pins on the MAX3421E more than
replace the µP pins necessary to implement the inter-
face. Although the MAX3421E SPI hardware includes
separate data-in (MOSI, master-out, slave-in) and data-
out (MISO, master-in, slave-out) pins, the SPI interface
can also be configured for the MOSI pin to carry bidi-
rectional data, saving an interface pin. This is referred
to as half-duplex mode.
Throughput by Allowing the SPI Master to
Transfer Data Concurrent with USB Transfers
Firmware
Features in Peripheral Operation
EP0: CONTROL (64 bytes)
EP1: OUT, BULK or INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, BULK or INTERRUPT, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, BULK or INTERRUPT (64 Bytes)
USB
Typical Application Circuits
REGULATOR
3.3V
MAX3421E
SPI
3, 4
INT
μP