MAX5945CAX+T Maxim Integrated Products, MAX5945CAX+T Datasheet - Page 26

• Manufacturer Part Number: MAX5945CAX+T
• Description: IC NETWORK PWR CTRL 36-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5945CAX+T

• Controller Type: Network Power Controller
• Interface: I²C
• Voltage - Supply: 3.3V
• Current - Supply: 4.2mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

function. OSC_FAIL generates an interrupt only if at
least one of the ACD_EN (R13h[7:4]) bits is set high.
A thermal-shutdown circuit monitors the temperature of
the die and resets the MAX5945 if the temperature
exceeds +150°C. TSD is set to 1 after the MAX5945
returns to normal operation. TSD is also set to 1 after
every UVLO reset.
When V
out (UVLO) threshold, the MAX5945 is in reset mode
and securely holds all ports off. When V
rise to above their respective UVLO thresholds, the
device comes out of reset as soon as the last supply
crosses the UVLO threshold. The last supply corre-
sponding UV and UVLO bits in the supply event regis-
ter will be set to 1.
A 1 in any supply event register’s bits forces R00h[7] to
1. As with any other events register, the supply event
register has two addresses. When read through the
R0Ah address, the content of the register is left
unchanged. When read through the CoR R0Bh
address, the register content will be cleared. A reset
Quad Network Power Controller
for Power-Over-LAN
Table 12a. Detection Result Decoding Chart
26
Table 12b. Classification Result
Decoding Chart
DET_ST_[2:0]
______________________________________________________________________________________
CLASS_[2:0]
000
001
010
011
100
101
110
111
DD
000
001
010
011
100
101
110
111
and/or |V
DETECTED
HIGH CAP
DET_OK
OPEN0
RHIGH
RLOW
EE
None
DCN
DCP
Unknown
1
2
3
4
Undefined (treated as CLASS 0)
0
Current limit (>I
| is below its undervoltage lock-
Detection status unknown
Positive DC supply connected at the port (AGND - V
High capacitance at the port (>5µF)
Low resistance at the port. R
Detection pass. 17kΩ > R
High resistance at the port. R
Open port (I < 12.5µA)
Negative DC supply connected to the port (V
CLASS RESULT
CILIM
)
DD
and |V
EE
PD
|
PD
> 28kΩ.
PD
< 17kΩ.
> 28kΩ.
sets R0Ah/R0Bh to 00100001 if V
V
The port status register (Table 12) records the results of
the detection and classification at the end of each phase
in three encoding bits each. R0Ch contains detection and
classification status of port 1. R0Dh corresponds to port
2, R0Eh corresponds to port 3 and R0Fh corresponds to
port 4. Tables 12a and 12b show the detection/classifica-
tion result decoding charts, respectively.
As a protection, when POFF_CL (R17h[3], Table 20) is
set to 1, the MAX5945 prohibits turning on power to the
port that returns a status 111 after classification. A reset
sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h.
PGOOD_ is set to 1 (Table 13) at the end of the power-up
startup period if the power-good condition is met (0 <
(V
remain valid for more than t
PGOOD_ is reset to 0 whenever the output falls out of the
power-good condition. A fault condition immediately
forces PGOOD_ low.
PWR_EN_ is set to 1 when the port power is turned on.
PWR_EN_ resets to 0 as soon as the port turns off. Any
transition of PGOOD_ and PWR_EN_ bits set the corre-
sponding bit in the power event registers R02h/R03h
(Table 7). A reset sets R10h = 00h.
A3, A2, A1, A0 (Table 14) represent the four LSBs of the
MAX5945 address (Table 3). During a reset, the device
latches into R11h. These four bits address from the cor-
responding inputs as well as the state of the MIDSPAN
and AUTO inputs. Changes to those inputs during nor-
mal operation are ignored.
The MAX5945 uses two bits for each port to set the mode
of operation (Table 15). Set the modes according to
Table 15a.
A reset sets R12h = AAAAAAAA where A represents
the latched-in state of the AUTO input prior to the reset.
Use software to change the mode of operation.
EE
OUT
or to 00010100 if V
DESCRIPTION
- V
EE)
OUT
< PG
- V
OUT_
EE
< 2V)
TH
< 1.65V)
). The power-good condition must
EE
comes up after V
PGOOD
DD
to assert PGOOD_.
comes up after
DD
.