DS21FT42 Maxim Integrated Products, DS21FT42 Datasheet - Page 69

• Manufacturer Part Number: DS21FT42
• Description: IC FRAMER T1 4X3 12CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FT42

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 225mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
(MSB)
RBOC
SYMBOL
SYMBOL
TMEND
THALF
RHALF
THALF
RBOC
RNE
RNE
TNF
RPE
RPS
RPE
POSITION
POSITION
HIMR.7
HIMR.6
HIMR.5
HIMR.4
HIMR.3
HIMR.2
HSR.3
HSR.2
HSR.1
HSR.0
RPS
RHALF
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Receive FIFO Not Empty. Set when the receive 64-byte
FIFO has at least one byte available for a read. The setting of
this bit prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64 byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64-byte
FIFO has at least one byte available. The setting of this bit
prompts the user to read the THIR register for details.
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
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RNE
THALF
TNF
TMEND
(LSB)