MAX782CBX Maxim Integrated Products, MAX782CBX Datasheet - Page 16

• Manufacturer Part Number: MAX782CBX
• Description: DC/DC Switching Controllers
• Manufacturer: Maxim Integrated Products

Specifications of MAX782CBX

• Number Of Outputs: 2
• Output Voltage: 3.3 V
• Output Current: 18 A
• Input Voltage: 5.5 V to 30 V
• Mounting Style: SMD/SMT
• Package / Case: SSOP-36
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Case: SSOP36
• Dc: 97+

Triple-Output Power-Supply
Controller for Notebook Computers
Table 3 lists two commercially available transformers
and parts for a custom transformer. The following
instructions show how to determine the transformer
parameters required for a custom design:
The transformer primary is specified just as the +3.3V
inductor, using V
(VDD) power must be added in as if it were part of the
primary. VDD current (I
and VPPB output currents. The total +5V power, P
is the sum of these powers:
where:
and:
so:
and the equivalent +5V output current, I
The primary inductance, L
where:
The highest peak primary current (I
total DC load current (I
AC primary current (I
current is typically chosen as 30% of the maximum DC
load current, so the peak primary current is 1.15 times
I
but results in higher losses and higher ripple.
The peak current in the primary at full load is given by:
Choose a core with an LI
I
16
TOTAL
LPEAK 2
I
LPEAK
______________________________________________________________________________________
L
I
LI
R
N, the primary-to-secondary turns ratio.
LPEAK
P
P
. A higher value of LIR allows smaller inductance,
2
, the primary inductance value
.
, the core’s energy rating
and R
P
P5 = V
P
V
I
VDD = VDD output voltage, 15V;
I
P
I
L
V
V
f = switching frequency, normally 300kHz;
I
LIR = ratio of primary peak-to-peak AC
current to average DC load current, typically 0.3.
= I
OUT
DD
TOTAL
TOTAL
, the peak primary current
P
TOTAL
DD
OUT
TOTAL
OUT
IN(MAX)
= ———————————————
TOTAL
S
= maximum VDD load current (A);
= VDD x I
, the primary and secondary resistances
= maximum +5V load current (A);
= output voltage, 5V;
= output voltage, 5V;
= maximum equivalent load current (A);
OUT
V
V
OUT
= P
= [(5V x I
= P5 + P
= (5V x I
OUT
IN(MAX)
= maximum input voltage;
+ —————————————.
LPP
TOTAL
x I
= +5.0V; but the secondary output
TOTAL
OUT
x (V
). The peak-to-peak AC primary
DD
V
DD
OUT
2
OUT
P
x f x I
DD
OUT
;
;
/ 5V
, is given by:
2 x f x L
parameter greater than L
) usually includes the VPPA
+5V Transformer (T1)
) plus half the peak-to-peak
IN(MAX)
) + (15V x I
x (V
) + (15V x I
TOTAL
IN(MAX
P
- V
x V
LPEAK
x LIR
OUT
TOTAL
) - V
IN(MAX)
DD
DD
)
) equals the
)
)] / 5V.
OUT
, is:
)
TOTAL
P
x
,
The winding resistances, R
as possible, preferably in the low milliohms. Use the
largest gauge wire that will fit on the core. The coil is
effectively in series with the load at all times, so the
resistive losses in the primary winding alone are
approximately (I
The minimum turns ratio, N
to accommodate the tolerance of the +5V supply. A
greater ratio will reduce efficiency of the VPP regulators.
Minimize the diode capacitance and the interwinding
capacitance, since they create losses through the
VDD shunt regulator. These are most significant when
the input voltage is high, the +5V load is heavy, and
there is no load on VDD.
Ensure the transformer secondary is connected with the
right polarity: A VDD supply will be generated with either
polarity, but proper operation is possible only with the cor-
rect polarity. Test for correct connection by measuring the
VDD voltage when VDD is unloaded and the input voltage
(V
indicated if VDD is maintained between 13V and 20V.
The sense resistors must carry the peak current in the
inductor, which exceeds the full DC load current.
The internal current limiting starts when the voltage
across the sense resistors exceeds 100mV nominally,
80mV minimum. Use the minimum value to ensure
adequate output current capability: For the +3.3V
supply, R1 = 80mV / (1.15 x I
R2 = 80mV/(1.15 x I
Since the sense resistance values (e.g. R1 = 25mΩ for
I
traces on a printed circuit board, trace resistance can
contribute significant errors. To prevent this, Kelvin
connect the CS_ and FB_ pins to the sense resistors;
i.e., use separate traces not carrying any of the induc-
tor or load current, as shown in Figure 5.
Run these traces parallel at minimum spacing from one
another. The wiring layout for these traces is critical for
stable, low-ripple outputs (see the Layout and
Grounding section).
The four N-channel power MOSFETs are usually iden-
tical and must be “logic-level” FETs; that is, they must
be fully on (have low r
source drive voltage. The MOSFET r
ideally be about twice the value of the sense resistor.
MOSFETs with even lower r
capacitance, which increases switching time and
transition losses.
OUT
IN
) is varied over its full range. Correct connection is
= 3A) are similar to a few centimeters of narrow
TOTAL
Current-Sense Resistors (R1, R2)
TOTAL
MOSFET Switches (N1-N4)
)
2
x R
MIN
DS(ON)
), assuming that LIR = 0.3.
P
P
.
and R
, is 5V:(15V-5V). Use 1:2.2
DS(ON)
OUT
) with only 4V gate-
); for the +5V supply,
S
, should be as low
have higher gate
DS(ON)
should