74HC373N,652 Philips Semiconductors, 74HC373N,652 Datasheet - Page 12

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74HC373N,652

Manufacturer Part Number
74HC373N,652
Description
LATCH; PDIP-20; LATCH LOGIC; 2 TO 6V; -40; +125; 6 TR; 6 TF
Manufacturer
Philips Semiconductors
Datasheet

Specifications of 74HC373N,652

Circuit Type
High Speed, Low-Power Schottky, Silicon Gate
Current, Supply
160 μA
Function Type
D-Type
Input Fall Time
6 ns
Input Rise Time
6 ns
Logic Function
Latch
Logic Type
CMOS
Number Of Circuits
Octal
Package Type
DIP-20
Special Features
Bus, Non-Inverting, Transparent, Tri-State
Temperature, Operating, Maximum
125 °C
Temperature, Operating, Minimum
-40 °C
Temperature, Operating, Range
-40 to +125 °C
Voltage, Supply
5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
Philips Semiconductors
Table 10:
Voltages are referenced to GND (ground = 0 V); C
[1]
74HC_HCT373_3
Product data sheet
Symbol Parameter
t
t
t
C
T
t
t
t
t
t
t
t
t
t
t
t
T
t
t
t
t
t
t
t
t
t
t
t
W
su
h
PHL
PLH
PZH
PZL
PHZ
PLZ
THL
TLH
W
su
h
PHL
PLH
PZH
PZL
PHZ
PLZ
THL
TLH
W
su
h
amb
amb
PD
,
,
,
,
,
,
,
,
C
P
f
f
C
V
N = number of inputs switching;
i
o
D
CC
= 40 C to +85 C
= 40 C to +125 C
PD
= input frequency in MHz;
L
(C
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
power dissipation capacitance
propagation delay
3-state output enable time OE to Qn V
3-state output disable time OE to Qn V
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
propagation delay
3-state output enable time OE to Qn V
3-state output disable time OE to Qn V
output transition time
pulse width LE HIGH
set-up time Dn to LE
hold time Dn to LE
PD
V
Dynamic characteristics 74HCT373
CC
Dn to Qn
LE to Qn
Dn to Qn
LE to Qn
2
V
CC
f
o
2
) = sum of outputs.
f
i
N + (C
L
V
CC
2
f
o
) where:
Conditions
V
V
V
per latch;
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
I
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
…continued
L
= GND to (V
= 50 pF unless otherwise specified; for test circuit see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V, see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
D
in W).
CC
Figure 10
Figure 9
Figure 11
Figure 11
Figure 8
Figure 9
Figure 10
Figure 10
Figure 8
Figure 9
Figure 11
Figure 11
Figure 8
Figure 9
Figure 10
Figure 8
Figure 8
Figure 11
Figure 11
1.5 V)
74HC373; 74HCT373
Octal D-type transparent latch; 3-state
[1]
Min
16
12
4
-
-
-
-
-
-
20
15
4
-
-
-
-
-
24
18
4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Typ
4
6
41
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
Figure
Max
-
-
-
-
38
40
40
38
15
-
-
-
45
48
48
45
18
-
-
-
12.
Unit
ns
ns
ns
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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