PIC16F88-I/P Microchip Technology Inc., PIC16F88-I/P Datasheet - Page 69

• Manufacturer Part Number: PIC16F88-I/P
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/P

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

6.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt-on-overflow from FFh to 00h
• Edge select for external clock
Additional information on the Timer0 module is
available in the “PICmicro
Reference Manual” (DS33023).
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Timer0
OPTION_REG register (see Register 2-2). Timer mode
is selected by clearing bit T0CS (OPTION_REG<5>).
In Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
FIGURE 6-1:
 2005 Microchip Technology Inc.
Note: T0CS, T0SE, PSA and PS2:PS0 bits are (OPTION_REG<5:0>).
WDT Enable bit
31.25 kHz
RA4/T0CKI/C2OUT
TIMER0 MODULE
Timer0 Operation
CLKO (= F
operation
WDT Timer
pin
OSC
Prescaler
16-bit
/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
is
T0SE
®
controlled
Mid-Range MCU Family
0
1
0
1
PSA
through
T0CS
M
U
X
M
U
X
the
8-bit Prescaler
0
8-to-1 MUX
1
0
Time-out
8
M U X
WDT
PSA
M
U
X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will incre-
ment, either on every rising or falling edge of pin RA4/
T0CKI/C2OUT. The incrementing edge is determined by
the
(OPTION_REG<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 6.3 “Using Timer0 with
an External Clock”.
The prescaler is mutually, exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 6.4
“Prescaler” details the operation of the prescaler.
6.2
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine before re-enabling this inter-
rupt. The TMR0 interrupt cannot awaken the processor
from Sleep, since the timer is shut off during Sleep.
Prescaler
1
Timer0
Timer0 Interrupt
Cycles
Sync
PSA
2
Source
PS2:PS0
PIC16F87/88
Edge
TMR0 reg
Data Bus
Set Flag bit TMR0IF
Select
8
DS30487C-page 67
on Overflow
bit,
T0SE