PIC16C74B-20I/L Microchip Technology Inc., PIC16C74B-20I/L Datasheet - Page 68

• Manufacturer Part Number: PIC16C74B-20I/L
• Description: 44 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20I/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16C63A/65B/73B/74B
11.2
In this mode, the USART uses standard non-
return-to-zero (NRZ) format (one START bit, eight or
nine data bits, and one STOP bit). The most common
data format is 8 bits. An on-chip, dedicated, 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSb first. The USART’s transmit-
ter and receiver are functionally independent, but use
the same data format and baud rate. The baud rate
generator produces a clock, either x16 or x64 of the bit
shift rate, depending on bit BRGH (TXSTA<2>). Parity
is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
the USART Transmit Flag bit TXIF (PIR1<4>) is set.
FIGURE 11-1:
DS30605C-page 68
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
CY
Interrupt
), the TXREG register is empty and
USART TRANSMIT BLOCK DIAGRAM
TXIF
TXEN
Baud Rate Generator
SPBRG
Baud Rate CLK
MSb
(8)
TX9D
TSR register
TX9
TXREG register
8
Data Bus
This interrupt can be enabled/disabled by setting/clear-
ing the USART Transmit Enable bit TXIE (PIE1<4>).
The flag bit TXIF will be set, regardless of the state of
enable bit TXIE and cannot be cleared in software. It
will reset only when new data is loaded into the TXREG
register. While flag bit TXIF indicates the status of the
TXREG register, another bit TRMT (TXSTA<1>) shows
the status of the TSR register. Status bit TRMT is a read
only bit, which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
Note 1: The TSR register is not mapped in data
LSb
0
2: Flag bit TXIF is set when enable bit TXEN
memory, so it is not available to the user.
is set. TXIF is cleared by loading TXREG.
TRMT
Pin Buffer
and Control
SPEN
2000 Microchip Technology Inc.
RC6/TX/CK pin