PIC16F84A-04/P Microchip Technology Inc., PIC16F84A-04/P Datasheet - Page 16

• Manufacturer Part Number: PIC16F84A-04/P
• Description: 18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F84A-04/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F84A
3.1
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore, it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
EXAMPLE 3-1:
3.2
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
EXAMPLE 3-2:
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment.
TABLE 3-1:
DS35007B-page 14
08h
09h
88h
89h
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
BCF
MOVLW
MOVWF
BSF
BSF
BCF
MOVF
Address
BSF
BCF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
Reading the EEPROM Data
Memory
Writing to the EEPROM Data
Memory
Shaded cells are not used by data EEPROM.
STATUS, RP0
CONFIG_ADDR
EEADR
STATUS, RP0
EECON1, RD
STATUS, RP0
EEDATA, W
EEDATA
EEADR
EECON1
EECON2 EEPROM Control Register 2
Name
STATUS, RP0
INTCON, GIE
EECON1, WREN ; Enable Write
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON, GIE
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
DATA EEPROM READ
DATA EEPROM WRITE
EEPROM Data Register
EEPROM Address Register
Bit 7
—
; Bank 0
;
; Address to read
; Bank 1
; EE Read
; Bank 0
; W = EEDATA
Bit 6
; Bank 1
; Disable INTs.
;
; Write 55h
;
; Write AAh
; Set WR bit
;
; Enable INTs.
—
begin write
Bit 5
—
EEIF
Bit 4
WRERR
Bit 3
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code exe-
cution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
3.3
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example 3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
Generally, the EEPROM write failure will be a bit which
was written as a ’0’, but reads back as a ’1’ (due to
leakage off the bit).
EXAMPLE 3-3:
READ
WREN
Bit 2
BCF
:
:
MOVF EEDATA,W
BSF
BSF
BCF
SUBWF EEDATA, W
BTFSS STATUS, Z
GOTO WRITE_ERR
Write Verify
Bit 1
WR
STATUS,RP0 ; Bank 0
STATUS,RP0 ; Bank 1
EECON1, RD
STATUS, RP0 ; Bank 0
WRITE VERIFY
Bit 0
RD
2001 Microchip Technology Inc.
; Any code
; can go here
; Must be in Bank 0
; YES, Read the
; value written
;
; Is the value written
; (in W reg) and
; read (in EEDATA)
; the same?
;
;
; Is difference 0?
; NO, Write error
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---0 x000 ---0 q000
---- ---- ---- ----
Power-on
Value on
Reset
Value on
all other
RESETS