DS80C320-QNG+ Dallas Semiconductor, DS80C320-QNG+ Datasheet - Page 24

• Manufacturer Part Number: DS80C320-QNG+
• Description: Microcontroller, 8051 Comp., 4 8-Bit I/O Ports, 64K ROM/RAM, 25 MHz, 5 V, PLCC44
• Manufacturer: Dallas Semiconductor

Specifications of DS80C320-QNG+

• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: UART
• Memory Type: ROMless
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 0 Bytes
• Ram Size: 256 Bytes
• Speed: 25 MHz
• Timers: 4-8-bit, 3-16-bit
• Voltage, Range: 4.25-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

MOVX CHARACTERISTICS—DS80C320
Note: t
t
MCS
Data Hold After Read
Data Float After Read
ALE Low to Valid Data In
Port 0 Address to Valid Data
In
Port 2 Address to Valid Data
In
ALE Low to
Port 0 Address Valid to
Port 2 Address Valid to
Data Valid to
Data Hold After Write
High
RD
RD
RD
RD
WR
WR
WR
for each Stretch selection.
Pulse Width
Low to Valid Data In
Low to Address Float
or
Pulse Width
Low
Low
MCS
PARAMETER
WR
is a time period related to the Stretch memory cycle selection. The following table shows the value of
High to ALE
RD
WR
or
Transition
M2
WR
0
0
0
0
1
1
1
1
RD
RD
Low
or
or
M1
0
0
1
1
0
0
1
1
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVWL1
AVWL2
t
AVDV1
AVDV2
WLWH
QVWX
WHQX
WHLH
RLDV
RHDX
RHDZ
LLWL
RLRH
LLDV
RLAZ
M0
0
1
0
1
0
1
0
1
2.5t
0.5t
1.5t
1.5t
24 of 40
2t
2t
2t
t
t
t
2t
t
t
3 machine cycles (default)
CLCL
CLCL
CLCL
t
MCS
MCS
CLCL
CLCL
CLCL
CLCL
MIN
CLCL
CLCL
CLCL
CLCL
CLCL
-9
VARIABLE CLOCK
0
0
MOVX CYCLES
-11
-11
-11
-10
-12
2 machine cycles
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
-11
-11
-10
-5
-7
-13
-8
-7
-9
1.5t
2.5t
2t
2.5t
3.5t
CLCL
0.5t
1.5t
2t
3t
CLCL
CLCL
t
(Note 5)
2t
t
CLCL
t
MAX
MCS
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
-31+t
CLCL
CLCL
10
-28+t
-34+t
-25
+11
-25
-5
-27
-5
-27
-32
+6
+8
MCS
MCS
MCS
12 t
16 t
20 t
24 t
28 t
4 t
8 t
t
MCS
CLCL
CLCL
0
UNITS
CLCL
CLCL
CLCL
CLCL
CLCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
MCS
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0
=0
>0