PIC16F690-E/P Microchip Technology Inc., PIC16F690-E/P Datasheet - Page 71

• Manufacturer Part Number: PIC16F690-E/P
• Description: 20 PIN, 7 KB FLASH, 256 RAM, 18 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F690-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 7 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 18
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.3
PORTB is a 4-bit wide, bidirectional port. The
corresponding data direction register is TRISB (Register
4-6). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 4-3 shows how to initialize PORTB. Reading
the PORTB register (Register 4-5) reads the status of the
pins, whereas writing to it will write to the PORT latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified and then written to the PORT
data latch.
The TRISB register controls the PORTB pin output
drivers, even when they are being used as analog inputs.
The user should ensure the bits in the TRISB register are
maintained set when using them as analog inputs. I/O
pins configured as analog input always read ‘0’.
EXAMPLE 4-3:
4.4
PORTB pins RB<7:4> on the device family device have
an interrupt-on-change option and a weak pull-up
option. The following three sections describe these
PORTB pin functions.
REGISTER 4-7:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-4
bit 3-0
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
BCF
Note:
R/W-x
RB7
PORTB and TRISB Registers
Additional PORTB Pin Functions
STATUS,RP0 ;Bank 0
STATUS,RP1 ;
PORTB
STATUS,RP0 ;Bank 1
FFh
TRISB
STATUS,RP0 ;Bank 0
The ANSELH register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
RB<7:4>: PORTB I/O Pin bit
1 = Port pin is > V
0 = Port pin is < V
Unimplemented: Read as ‘0’
R/W-x
RB6
PORTB: PORTB REGISTER
INITIALIZING PORTB
;Init PORTB
;Set RB<7:4> as inputs
;
IH
IL
W = Writable bit
‘1’ = Bit is set
R/W-x
PIC16F631/677/685/687/689/690
RB5
R/W-x
RB4
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
4.4.1
Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:4> enable or
disable each pull-up (see Register 4-9). Each weak
pull up is automatically turned off when the port pin is
configured as an output. All pull-ups are disabled on a
Power-on Reset by the RABPU bit of the OPTION
register.
4.4.2
Four of the PORTB pins are individually configurable as
an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 4-10. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the present
value is compared with the old value latched on the last
read of PORTB to determine which bits have changed
or mismatch the old value. The ‘mismatch’ outputs are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a)
b)
A mismatch condition will continue to set flag bit RABIF.
Reading or writing PORTB will end the mismatch
condition and allow flag bit RABIF to be cleared. The latch
holding the last read value is not affected by a MCLR nor
Brown-out Reset. After these Resets, the RABIF flag will
continue to be set if a mismatch is present.
U-0
—
Note:
Any read or write of PORTB. This will end the
mismatch condition.
Clear the flag bit RABIF.
WEAK PULL-UPS
INTERRUPT-ON-CHANGE
If a change on the I/O pin should occur when
the read operation is being executed (start of
the Q2 cycle), then the RABIF interrupt flag
may not get set. Furthermore, since a read
or write on a port affects all bits of that port,
care must be taken when using multiple pins
in Interrupt-on-Change mode. Changes on
one pin may not be seen while servicing
changes on another pin.
U-0
—
x = Bit is unknown
U-0
—
DS41262C-page 69
U-0
—
bit 0