DS21348TN+ Maxim Integrated Products, DS21348TN+ Datasheet

IC LIU T1/E1/J1 3.3V 44-TQFP

DS21348TN+

Manufacturer Part Number
DS21348TN+
Description
IC LIU T1/E1/J1 3.3V 44-TQFP
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet

Specifications of DS21348TN+

Number Of Drivers/receivers
1/1
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
44-TQFP, 44-VQFP
Product
Framer
Number Of Transceivers
1
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
100 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
FEATURES
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
www.maxim-ic.com
Complete E1, T1, or J1 Line Interface Unit
(LIU)
Supports Both Long-Haul And Short-Haul
Trunks
Internal Software-Selectable Receive-Side
Termination for 75Ω/100Ω/120Ω
3.3V Power Supply
32-Bit or 128-Bit Crystal-Less Jitter
Attenuator Requires Only a 2.048MHz
Master Clock for Both E1 and T1 with
Option to Use 1.544MHz for T1
Generates the Appropriate Line Build-Outs,
with and without Return loss, for E1 and
DSX-1 and CSU Line Build-Outs for T1
AMI, HDB3, and B8ZS, Encoding/Decoding
16.384MHz, 8.192MHz, 4.096MHz, or
2.048MHz Clock Output Synthesized to
Recovered Clock
Programmable Monitor Mode for Receiver
Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
Generates/Detects In-Band Loop Codes,
1 to 16 Bits Including CSU Loop Codes
8-Bit Parallel or Serial Interface with
Optional Hardware Mode
Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
Detects/Generates Blue (AIS) Alarms
NRZ/Bipolar Interface for Tx/Rx Data I/O
Transmit Open-Circuit Detection
Receive Carrier Loss (RCL) Indication
(G.775)
High-Impedance State for TTIP and TRING
50mA (RMS) Current Limiter
1 of 76
3.3V E1/T1/J1 Line Interface
PIN CONFIGURATIONS
ORDERING INFORMATION
+ Denotes lead-free/RoHS-compliant package.
DS21348TN
DS21348TN+
DS21348T
DS21348T+
DS21348GN
DS21348GN+
DS21348G
DS21348G+
DS21Q348N
DS21Q348
PART
TOP VIEW
See Section
CHANNEL
1
DS21348/DS21Q348
Single
Single
Single
Single
Single
Single
Single
Single
Four
Four
8
44
for 144-pin CSBGA pinout.
(7mm x 7mm)
DS21348
49 CSBGA
44 TQFP
DS21Q348
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
RANGE
TEMP
1 1 1
REV: 011206
PRELMINARY
44 TQFP
44 TQFP
44 TQFP
44 TQFP
49 CSBGA
49 CSBGA
49 CSBGA
49 CSBGA
144 CSBGA
144 CSBGA
PIN-PACKAGE

Related parts for DS21348TN+

DS21348TN+ Summary of contents

Page 1

... E1/T1/J1 Line Interface PIN CONFIGURATIONS 44 TOP VIEW 1 DS21348 44 TQFP DS21Q348 49 CSBGA (7mm x 7mm) See Section 8 for 144-pin CSBGA pinout. ORDERING INFORMATION PART CHANNEL DS21348TN Single DS21348TN+ Single DS21348T Single DS21348T+ Single DS21348GN Single DS21348GN+ Single DS21348G Single DS21348G+ Single DS21Q348N Four DS21Q348 Four + Denotes lead-free/RoHS-compliant package ...

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DETAILED DESCRIPTION The DS21348 is a complete selectable line interface unit (LIU) for short-haul and long-haul applications. Throughout the data sheet represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can ...

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INTRODUCTION.................................................................................................................. 6 1.1 DOCUMENT REVISION HISTORY...............................................................................................6 2. PIN DESCRIPTION............................................................................................................ 10 2 ........................................................................................................................14 IN ESCRIPTIONS 3. HARDWARE MODE .......................................................................................................... 25 3 .............................................................................................................................25 EGISTER AP 3 ARALLEL ORT PERATION 3 ERIAL ...

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Figure 1-1. DS21348 Block Diagram ..........................................................................................................7 Figure 1-2. Receive Logic...........................................................................................................................8 Figure 1-3. Transmit Logic..........................................................................................................................9 Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = (TQFP Package) ..................................22 Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, ...

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Table 2-1. Bus Interface Selection ...........................................................................................................10 Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10 Table 2-3. Pin Assignment in Serial Port Mode ........................................................................................11 Table 2-4. Pin Assignment in Hardware Mode .........................................................................................12 Table 2-5. Pin Descriptions in Parallel Port Mode ...

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INTRODUCTION The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use internal ...

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Figure 1-1. DS21348 Block Diagram 2 2 Power Connections RRING RTIP TRING TTIP BIS1 MUX (the Serial, Parallel, and Hardware Interfaces share device pins) BIS0 Serial Interface JACLK Jitter Attenuator MUX VCO / PLL Unframed All Ones Insertion Control and ...

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Figure 1-2. Receive Logic Clock Invert From Routed to Remote All Blocks CCR2.0 Loopback CCR2 Zero Detect 16 Zero Detect RIR1.7 RIR1.6 NRZ Data B8ZS/HDB3 Decoder BPV/CV/EXZ All Ones Loop Code Detector Detector CCR6.2/ RIR1.5 CCR6.0/ CCR6.1 ...

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Figure 1-3. Transmit Logic CCR1.6 OR Gate CCR3.1 1 BPV mux To Insert Remote Loopback 0 Routed to All Blocks CCR2.2 CCR3.0 B8ZS/ Logic HDB3 Error Coder Insert 0 0 mux 1 mux OR Gate RCLK 1 AND CCR1.1 Gate ...

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PIN DESCRIPTION The DS21348 can be controlled in a parallel port mode, serial port mode, or hardware mode Table 2-3, and Table 2-4). Table 2-1. Bus Interface Selection BIS1 BIS0 ...

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PIN DS21348T DS21348G Table 2-3. Pin ...

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PIN DS21348T DS21348G ...

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PIN DS21348T DS21348G ...

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Pin Descriptions Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering) NAME PIN I ALE (AS) 4 BIS0/BIS1 32/33 BPCLK D0/AD0 ...

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NAME PIN I/O PBTS 44 I RCLK (DS RCL LOTC RNEG 39 O RPOS 38 O RTIP/ 27/28 I RRING TCLK 43 I TEST 26 I TNEG 42 I TPOS 41 I FUNCTION ...

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NAME PIN I/O TTIP/ 34/37 TRING VDD 21/36 — VSM 20 VSS 22/35 — WR (R/W) 3 Table 2-6. Pin Descriptions in Serial Port Mode (Sorted By Pin Name, DS21348T Pin Numbering) NAME PIN I/O BIS0/BIS1 32/33 BPCLK 31 CS ...

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NAME PIN I/O RCLK 40 O RCL/LOTC 25 O RNEG 39 O RPOS 38 O RTIP/ 27/28 RRING SCLK 5 SDI 6 SDO 7 O TCLK 43 TEST 26 TNEG 42 TPOS 41 TTIP/TRIN 34/ VDD 21/36 — ...

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Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering) NAME PIN I/O BIS0/BIS1 32/33 BPCLK 31 CES 12 DJA 8 EGL 1 ETS 2 HBE 11 HRST 29 JAMUX 9 JAS 10 L0/L1/L2 7/6/5 LOOP0/ ...

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NAME PIN I/O MCLK 30 I MM0/MM1 18/ — I NRZE 3 I PBEO 24 O RCLK 40 O RCL 25 O RNEG 39 O RPOS 38 O RT0/RT1 44/23 I RTIP/ 27/28 I RRING SCLKE 4 I ...

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NAME PIN I/O TEST 26 TNEG 42 TPD 13 TPOS 41 TTIP/TRING 34/37 TX0/TX1 14/15 VDD 21/36 — VSM 20 VSS 22/35 — Note: G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require ...

Page 21

Table 2-8. Loopback Control in Hardware Mode LOOPBACK SYMBOL Remote Loopback Local Loopback Analog Loopback No Loopback Table 2-9. Transmit Data Control in Hardware Mode TRANSMIT DATA SYMBOL Transmit Unframed TUA1 All Ones Transmit Alternating TAOZ Ones and Zeros Transmit ...

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Table 2-13. MCLK Selection MCLK JAMUX (MHz) (CCR1.3) 2.048 0 2.048 1 1.544 0 Figure 2-1. Parallel Port Mode Pinout (BIS1 = 0, BIS0 = (TQFP Package (DS (R/W) 4 ALE ...

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Figure 2-2. Serial Port Mode Pinout (BIS1 = 1, BIS0 = 0) (TQFP Package SCLK 6 SDI 7 SDO 8 ICES 9 OCES BIS1 ...

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Figure 2-3. Hardware Mode Pinout (BIS1 = 1, BIS0 = 1) (TQFP Package) 1 EGL 2 ETS 3 NRZE 4 SCLKE DJA 9 JAMUX 10 JAS 11 HBE BIS1 33 BIS0 32 BPCLK ...

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HARDWARE MODE In hardware mode (BIS1 = 1, BIS0 = 1), pins 1–19, 23, 25, 31, and 44 are redefined to be used for initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. ...

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Parallel Port Operation When using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = ...

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Figure 3-1. Serial Port Operation for Read Access ( Mode 1 ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) SCLK ...

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Figure 3-4. Serial Port Operation for Read Access Mode 4 ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) SCLK SDI A0 ...

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CONTROL REGISTERS CCR1 (00H): COMMON CONTROL REGISTER 1 (MSB) ETS NRZE RCLA SYMBOL POSITION ETS CCR1.7 NRZE CCR1.6 RCLA CCR1.5 ECUE CCR1.4 JAMUX CCR1.3 TTOJ CCR1.2 TTOR CCR1.1 LOTCMC CCR1.0 ECUE JAMUX DESCRIPTION E1/T1 Select ...

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Table 4-1. MCLK Selection MCLK JAMUX (MHz) (CCR1.3) 2.048 0 2.048 1 1.544 0 CCR2 (01H): COMMON CONTROL REGISTER 2 (MSB) P25S n/a SCLD SYMBOL POSITION P25S CCR2.7 - CCR2.6 SCLD CCR2.5 CLDS CCR2.4 RHBE CCR2.3 THBE CCR2.2 TCES CCR2.1 ...

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CCR3 (02H): COMMON CONTROL REGISTER 3 (MSB) TUA1 ATUA1 TAOZ SYMBOL POSITION TUA1 CCR3.7 ATUA1 CCR3.6 TAOZ CCR3.5 TPRBSE CCR3.4 TLCE CCR3.3 LIRST CCR3.2 IBPV CCR3.1 IBE CCR3.0 TPRBSE TLCE DESCRIPTION Transmit Unframed All Ones. The polarity of this bit ...

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Device Power-Up and Reset The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and information registers. CCR3.7 (TUA1 results in the LIU transmitting unframed all ones. After the power ...

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CCR5 (04H): COMMON CONTROL REGISTER 5 (MSB) BPCS1 BPCS0 SYMBOL POSITION BPCS1 CCR5.7 BPCS0 CCR5.6 MM1 CCR5.5 MM0 CCR5.4 RSCLKE CCR5.3 TSCLKE CCR5.2 RT1 CCR5.1 RT0 CCR5.0 MM1 MM0 RSCLKE DESCRIPTION Backplane Clock Select 1. See Backplane Clock Select 0. ...

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Table 4-3. Backplane Clock Select BPCS1 BPCS0 (CCR5.7) (CCR5. Table 4-4. Monitor Gain Settings MM1 MM0 (CCR5.5) (CCR5. Table 4-5. Internal Rx Termination Select ...

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CCR6 (05H): COMMON CONTROL REGISTER 6 (MSB) LLB RLB SYMBOL POSITION DESCRIPTION LLB CCR6.7 Local Loopback. In Local Loopback (LLB), transmit data will be looped back to the receive path passing through the jitter attenuator enabled. Data ...

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STATUS REGISTERS There are three registers that contain information on the current real-time status of the device, Status Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has occurred (or is occurring), the appropriate ...

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SR (06H): STATUS REGISTER (MSB) LUP LDN LOTC SYMBOL POSITION DESCRIPTION LUP SR.7 (latched) LDN SR.6 (latched) LOTC SR.5 (real time) RUA1 SR.4 (latched) RCL SR.3 (latched) TCLE SR.2 (real time) TOCD SR.1 (real time) PRBSD SR.0 (real time) RUA1 ...

Page 38

IMR (07H): INTERRUPT MASK REGISTER (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR.7 LDN IMR.6 LOTC IMR.5 RUA1 IMR.4 RCL IMR.3 TCLE IMR.2 TOCD IMR.1 PRBSD IMR.0 RUA1 RCL DESCRIPTION Loop-Up Code Detected interrupt masked 1 = interrupt ...

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RIR1 (08H): RECEIVE INFORMATION REGISTER 1 (MSB) ZD 16ZD SYMBOL POSITION ZD RIR1.7 (latched) 16ZD RIR1.6 (latched) HBD RIR1.5 (latched) RCLC RIR1.4 (latched) RUA1C RIR1.3 (latched) JALT RIR1.2 (latched) N/A RIR1.1 N/A RIR1.0 HBD RCLC RUA1C DESCRIPTION Zero Detect. Set ...

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RIR2 (09H): RECEIVE INFORMAION REGISTER 2 (MSB) RL3 RL2 SYMBOL POSITION RL3 RIR2.7 (real time) RL2 RIR2.6 (real time) RL1 RIR2.5 (real time) RL0 RIR2.4 (real time) N/A RIR2.3 N/A RIR2.2 ARLB RIR2.1 (real time) SEC RIR2.0 (latched) Table 5-2. ...

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DIAGNOSTICS 6.1 In-Band Loop Code Generation and Detection The DS21348 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in length. To transmit a pattern, the user will load the pattern ...

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LENGTH SELECTED TC1 TC0 Table 6-2. Receive Code Length RUP2/RDN2 RUP1/ RDN1 TCD1 (0BH): TRANSMIT CODE ...

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TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2 (MSB) C15 C14 SYMBOL POSITION C15 TCD2.7 C14 TCD2.6 C13 TCD2.5 C12 TCD2.4 C11 TCD2.3 C10 TCD2.2 C9 TCD2.1 C8 TCD2.0 RUPCD1 (0DH): RECEIVE UP CODE DEFINITION REGISTER 1 (MSB SYMBOL ...

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RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2 (MSB) C15 C14 SYMBOL POSITION C15 RUPCD2.7 C14 RUPCD2.6 C13 RUPCD2.5 C12 RUPCD2.4 C11 RUPCD2.3 C10 RUPCD2.2 C9 RUPCD2.1 C8 RUPCD2.0 RDNCD1 (0FH): RECEIVE DOWN CODE DEFINITION REGISTER 1 (MSB ...

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RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2 (MSB) C15 C14 SYMBOL POSITION C15 RDNCD2.7 C14 RDNCD2.6 C13 RDNCD2.5 C12 RDNCD2.4 C11 RDNCD2.3 C10 RDNCD2.2 C9 RDNCD2.1 C8 RDNCD2.0 C13 C12 C11 DESCRIPTION Receive Down Code Definition Bit 15 Receive ...

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Loopbacks 6.2.1 Remote Loopback (RLB) When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data from the clock/data recovery state machine will be looped back to the transmit path passing through the jitter ...

Page 47

PRBS Generation and Detection Setting TPRBSE (CCR3. enables the DS21348 to transmit a 2 Random Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the DS21348 will always search for these PRBS ...

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Table 6-4. Function of ECRS Bits and RNEG Pin ECRS2 ECRS1 (CCR1.7) (CCR6.2) (CCR6. RNEG outputs error data only ...

Page 49

ANALOG INTERFACE 7.1 Receiver The DS21348 contains a digital clock recovery system. The DS21348 couples to the receive twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See details. Figure 7-1, Figure ...

Page 50

Transmitter The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the line. The waveforms created by the DS21348 meet the latest ...

Page 51

G.703 Synchronization Signal The DS21348 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703(10/98). To use the DS21348 in this mode, set the Receive Synchronization Clock Enable (CCR5. The DS21348 can ...

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Figure 7-1. Basic Interface Transmit Line N:1 (larger winding toward the network) Receive Line 1:1 NOTES: 1) All resistor values are ±1 applications, the Rt resistors are used to increase the transmitter return loss return loss is ...

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Figure 7-2. Protected Interface Using Internal Receive Termination (optional) Rp Fuse Transmit Line Fuse Rp N:1 (larger winding toward the network) Rp Fuse Receive Line Fuse Rp 1:1 (optional) NOTES: 1. All resistor values are ±1 ...

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Figure 7-3. Protected Interface Using External Receive Termination (optional) Rp Fuse Transmit Line Fuse Rp N:1 (larger winding toward the network) Rp Fuse Receive Line Fuse Rp (optional) NOTES: 1. All resistor values are ±1 0.1µF. 3. ...

Page 55

Figure 7-4. E1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 194ns 219ns -150 -100 - TIME (ns 269ns G.703 Template 100 150 ...

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Figure 7-5. T1 Transmit Pulse Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 T1.102/87, T1.403, -0.2 CB 119 (Oct. 79), & I.431 Template -0.3 -0.4 -0.5 -500 -400 -300 MAXIMUM CURVE UI -0.77 ...

Page 57

Figure 7-6. Jitter Tolerance 1k 100 10 1 0.1 1 Figure 7-7. Jitter Attenuation 0dB -20dB -40dB -60dB 1 DS21348 TR 62411 (Dec. 90) Tolerance ITU-T G.823 10 100 1k FREQUENCY (Hz) TBR12 Prohibited Area 100 1K ...

Page 58

DS21Q348 QUAD LIU The DS21Q348 is a quad version of the DS21348G utilizing CSBGA on carrier packaging technology. The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in this package. Table 8-1. ...

Page 59

PARALLEL PIN I/O PORT MODE F9 O RCL/LOTC3 J7 O RCL/LOTC4 A10 B11 F10 ...

Page 60

PARALLEL PIN I/O PORT MODE F12 I L12 I J5 — D2 — G9 — M9 — L5 — E4 — D8 — J8 — J4 — D1 — E9 — L10 — M4 — F4 — D9 — H9 ...

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Figure 8-1. 144-CSBGA (17mm x 17mm) Pinout RTIP1 TTIP1 RRING1 TRING1 VSS2 VDD2 CS2 E RPOS2 RNEG2 D3/AD3 F RCLK2 TPOS2 D1/AD1 G TPOS1 RNEG1 PEBO2 WR H ...

Page 62

DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V Operating Temperature Range for DS21348TN……………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………….-55°C to +125°C Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification This is a stress rating only and ...

Page 63

THERMAL CHARACTERISTICS Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package PARAMETER Ambient Temperature Junction Temperature Theta-JA (θ Still Air JA Theta-JC (θ Still Air JC NOTES: 1) The package is mounted on a four-layer JEDEC-standard test board. ...

Page 64

AC CHARACTERISTICS Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) = 3.3V ± 5 -40°C to +85°C.) (See DD A PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, ...

Page 65

Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) ALE t ASD AD0-AD7 Figure 11-2. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) ALE t ASD ...

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Figure 11-3. Motorola Bus Timing (PBTS = 1, BIS1 = 0, BIS0 = ASD R/W AD0-AD7 (read) CS AD0-AD7 (write) PW ASH t ASED t RWS t t DDR ASL t AHL t CS ...

Page 67

Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1) = 3.3V ± 5 -40°C to +85°C.) (See DD A Figure 11-7.) PARAMETER Setup Time for A0 to A4, Valid to CS Active Setup Time ...

Page 68

Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) A0 ...

Page 69

Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = R/W CS 0ns min. DS Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = ...

Page 70

Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) = 3.3V ± 5 -40°C to +85°C.) (See DD A PARAMETER Setup Time CS to SCLK Setup Time SDI to SCLK Hold Timfe SCLK to SDI ...

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Table 11-4. AC Characteristics—Receive Side = 3.3V ± 5 -40°C to +85°C.) (See DD A PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width Delay RCLK to RPOS, RNEG, PBEO, RBPV Valid NOTES mode. 2) ...

Page 72

Table 11-5. AC Characteristics—Transmit Side = 3.3V ± 5 -40°C to +85°C PARAMETER TCLK Period TCLK Pulse Width TPOS/TNEG Setup to TCLK Falling or Rising TPOS/TNEG Hold from TCLK Falling or Rising TCLK Rise and ...

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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 12.1 44-Pin TQFP (56-G4012-001) SEE DETAIL "A" ...

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CSGBA (7mm x 7mm) (56-G6006-001 ...

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CSBGA (17mm x 17mm) (56-G6011-001) A1 CORNER 3 Y 17. 1.27 13.97 0.20 1.52 4X 1.52 DETAIL A 0.76 DETAIL DS21348/DS21Q348 A1 CORNER ...

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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation. SOLDER BALL φ ...

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