PIC16C74B-20/L Microchip Technology Inc., PIC16C74B-20/L Datasheet - Page 51

• Manufacturer Part Number: PIC16C74B-20/L
• Description: 44 PIN, 7 KB OTP, 192 RAM, 33 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C74B-20/L

• A/d Inputs: 8-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 33
• Interface: I2C/SPI/USART
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 4 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2.5-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the fol-
lowing and is configured using CCPxCON<3:0>:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the previous captured value is overwritten by the
new captured value.
9.1.1
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
FIGURE 9-1:
RC2/CCP1
Note:
2000 Microchip Technology Inc.
pin
Capture Mode
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
CCP PIN CONFIGURATION
Edge Detect
Q’s
Prescaler
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
PIC16C63A/65B/73B/74B
9.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
9.1.4
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 9-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS ; Load the W reg with
CCP1CON
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
CCP PRESCALER
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; the new prescaler
; move value and CCP ON
; Load CCP1CON with this
; value
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